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Zephyr API Documentation 4.4.99
A Scalable Open Source RTOS
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RISCV specific kernel interface header. More...
#include <zephyr/arch/riscv/thread.h>#include <zephyr/arch/exception.h>#include <zephyr/arch/riscv/irq.h>#include <zephyr/arch/riscv/sys_io.h>#include <zephyr/arch/common/sys_bitops.h>#include <zephyr/arch/common/ffs.h>#include <zephyr/arch/riscv/syscall.h>#include <zephyr/irq.h>#include <zephyr/sw_isr_table.h>#include <zephyr/devicetree.h>#include <zephyr/arch/riscv/csr.h>#include <zephyr/sys/util.h>#include <zephyr/sys/slist.h>#include <zephyr/arch/riscv/error.h>Go to the source code of this file.
Data Structures | |
| struct | k_mem_partition_attr_t |
| struct | arch_mem_domain |
Macros | |
| #define | ARCH_STACK_PTR_ALIGN 16 |
| #define | ARCH_THREAD_STACK_RESERVED |
| #define | ARCH_THREAD_STACK_SIZE_ADJUST(size) |
| #define | ARCH_THREAD_STACK_OBJ_ALIGN(size) |
| #define | RV_REGSIZE 4 |
| #define | RV_REGSHIFT 2 |
| #define | MSTATUS_IEN (1UL << 3) |
| #define | MSTATUS_MPP_U (PRV_U << 11) |
| mstatus MPP field value for User mode | |
| #define | MSTATUS_MPP_S (PRV_S << 11) |
| mstatus MPP field value for Supervisor mode | |
| #define | MSTATUS_MPP_M (PRV_M << 11) |
| mstatus MPP field value for Machine mode | |
| #define | MSTATUS_MPIE_EN (1UL << 7) |
| #define | MSTATUS_FS_OFF (0UL << 13) |
| #define | MSTATUS_FS_INIT (1UL << 13) |
| #define | MSTATUS_FS_CLEAN (2UL << 13) |
| #define | MSTATUS_FS_DIRTY (3UL << 13) |
| #define | RV_STATUS_DEF_RESTORE (MSTATUS_MPP_M | MSTATUS_MPIE_EN) |
| Default status register value to restore when starting a new thread. | |
| #define | RV_STATUS_PP MSTATUS_MPP |
| Previous-privilege field mask in the status CSR (M-mode: MPP). | |
| #define | RV_STATUS_PP_U PRV_U |
| Previous-privilege field value representing User mode (M-mode). | |
| #define | K_MEM_PARTITION_P_RW_U_RW |
| #define | K_MEM_PARTITION_P_RW_U_RO |
| #define | K_MEM_PARTITION_P_RW_U_NA |
| #define | K_MEM_PARTITION_P_RO_U_RO |
| #define | K_MEM_PARTITION_P_RO_U_NA |
| #define | K_MEM_PARTITION_P_NA_U_NA |
| #define | K_MEM_PARTITION_P_RWX_U_RWX |
| #define | K_MEM_PARTITION_P_RX_U_RX |
| #define | RV_STATUS_CSR "mstatus" |
| Name of the interrupt-status CSR as a string literal (M-mode). | |
| #define | RV_STATUS_IE MSTATUS_IEN |
| Interrupt-enable bit in the status CSR (M-mode: MIE). | |
| #define | RV_STATUS_PIE MSTATUS_MPIE_EN |
| Previous interrupt-enable bit in the status CSR (M-mode: MPIE). | |
Functions | |
| static ALWAYS_INLINE unsigned int | arch_irq_lock (void) |
| static ALWAYS_INLINE void | arch_irq_unlock (unsigned int key) |
| static ALWAYS_INLINE bool | arch_irq_unlocked (unsigned int key) |
| static ALWAYS_INLINE bool | arch_cpu_irqs_are_enabled (void) |
| Implementation of arch_cpu_irqs_are_enabled. | |
| static ALWAYS_INLINE void | arch_nop (void) |
| uint32_t | sys_clock_cycle_get_32 (void) |
| static uint32_t | arch_k_cycle_get_32 (void) |
| uint64_t | sys_clock_cycle_get_64 (void) |
| static uint64_t | arch_k_cycle_get_64 (void) |
RISCV specific kernel interface header.
This header contains the RISCV specific kernel interface. It is included by the kernel interface architecture-abstraction header (include/zephyr/arch/cpu.h).
| #define ARCH_STACK_PTR_ALIGN 16 |
| #define ARCH_THREAD_STACK_OBJ_ALIGN | ( | size | ) |
| #define ARCH_THREAD_STACK_RESERVED |
| #define ARCH_THREAD_STACK_SIZE_ADJUST | ( | size | ) |
| #define K_MEM_PARTITION_P_NA_U_NA |
| #define K_MEM_PARTITION_P_RO_U_NA |
| #define K_MEM_PARTITION_P_RO_U_RO |
| #define K_MEM_PARTITION_P_RW_U_NA |
| #define K_MEM_PARTITION_P_RW_U_RO |
| #define K_MEM_PARTITION_P_RW_U_RW |
| #define K_MEM_PARTITION_P_RWX_U_RWX |
| #define K_MEM_PARTITION_P_RX_U_RX |
| #define MSTATUS_FS_CLEAN (2UL << 13) |
| #define MSTATUS_FS_DIRTY (3UL << 13) |
| #define MSTATUS_FS_INIT (1UL << 13) |
| #define MSTATUS_FS_OFF (0UL << 13) |
| #define MSTATUS_IEN (1UL << 3) |
| #define MSTATUS_MPIE_EN (1UL << 7) |
| #define MSTATUS_MPP_M (PRV_M << 11) |
mstatus MPP field value for Machine mode
| #define MSTATUS_MPP_S (PRV_S << 11) |
mstatus MPP field value for Supervisor mode
| #define MSTATUS_MPP_U (PRV_U << 11) |
mstatus MPP field value for User mode
| #define RV_REGSHIFT 2 |
| #define RV_REGSIZE 4 |
| #define RV_STATUS_CSR "mstatus" |
Name of the interrupt-status CSR as a string literal (M-mode).
| #define RV_STATUS_DEF_RESTORE (MSTATUS_MPP_M | MSTATUS_MPIE_EN) |
Default status register value to restore when starting a new thread.
This comes from openisa_rv32m1, but doesn't seem to hurt on other platforms:
In S-mode (CONFIG_RISCV_S_MODE), use the sstatus equivalents:
| #define RV_STATUS_IE MSTATUS_IEN |
Interrupt-enable bit in the status CSR (M-mode: MIE).
| #define RV_STATUS_PIE MSTATUS_MPIE_EN |
Previous interrupt-enable bit in the status CSR (M-mode: MPIE).
| #define RV_STATUS_PP MSTATUS_MPP |
Previous-privilege field mask in the status CSR (M-mode: MPP).
| #define RV_STATUS_PP_U PRV_U |
Previous-privilege field value representing User mode (M-mode).
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Implementation of arch_cpu_irqs_are_enabled.
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