Driver Configuration Options¶
Kconfig files describe build-time configuration options (called symbols
in Kconfig-speak), how they’re grouped into menus and sub-menus, and
dependencies between them that determine what configurations are valid.
Kconfig files appear throughout the directory tree. For example,
subsys/power/Kconfig defines power-related options.
This documentation is generated automatically from the Kconfig files by
the gen_kconfig_rest.py script. Click on symbols for more
information.
Configuration Options¶
Symbol name |
Help/prompt |
|---|---|
Second level interrupts are used to increase the number of addressable interrupts in a system. |
|
This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
|
This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
|
This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
|
This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
|
This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
|
This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
|
This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
|
This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
|
This is the offset in _sw_isr_table, the generated ISR handler table, where storage for 2nd level interrupt ISRs begins. This is typically allocated after ISRs for level 1 interrupts. |
|
Third level interrupts are used to increase the number of addressable interrupts in a system. |
|
This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
|
This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
|
This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
|
This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
|
This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
|
This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
|
This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
|
This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
|
This is the offset in _sw_isr_table, the generated ISR handler table, where storage for 3rd level interrupt ISRs begins. This is typically allocated after ISRs for level 2 interrupts. |
|
Enable ADC (Analog to Digital Converter) driver configuration. |
|
This option enables the asynchronous API calls. |
|
Enable LMP90xxx ADC driver. The LMP90xxx is a multi-channel, low power sensor analog frontend (AFE). |
|
Priority level for the internal ADC data acquisition thread. |
|
Size of the stack used for the internal data acquisition thread. |
|
Use Cyclic Redundancy Check (CRC) to verify the integrity of the data read from the LMP90xxx. |
|
Enable GPIO child device support in the LMP90xxx ADC driver. The GPIO functionality is handled by the LMP90xxx GPIO driver. |
|
LMP90xxx ADC device driver initialization priority. |
|
Enable MCP3204/MCP3208 ADC driver. The MCP3204/MCP3208 are 4/8 channel 12-bit A/D converters with SPI interface. |
|
Priority level for the internal ADC data acquisition thread. |
|
Size of the stack used for the internal data acquisition thread. |
|
MCP320x ADC device driver initialization priority. |
|
Enable the MCUX ADC12 driver. |
|
Enable the MCUX ADC16 driver. |
|
Divide ratio is 1 |
|
Divide ratio is 2 |
|
Divide ratio is 4 |
|
Divide ratio is 8 |
|
Alternate reference pair |
|
Default voltage reference pair V_REFH and V_REFL |
|
Enable the MCUX LPADC driver. |
|
Enable support for NPCX ADC driver. In NPCX7 series, it includes a 10-bit resolution Analog-to-Digital Converter (ADC). Up to 10 voltage inputs can be measured and a internal voltage reference (VREF), 2.816V (typical) is used for measurement. |
|
Enable support for nrfx ADC driver for nRF51 MCU series. |
|
Number of ADC channels to be supported by the driver. Each channel needs a dedicated structure in RAM that stores the ADC settings to be used when sampling this channel. |
|
Enable support for nrfx SAADC driver. |
|
Enable Atmel SAM0 MCU Family Analog-to-Digital Converter (ADC) driver. |
|
Enable Atmel SAM MCU Family Analog-to-Digital Converter (ADC) driver based on AFEC module. |
|
Enable ADC Shell for testing. |
|
Enable the driver implementation for the stm32xx ADC |
|
Enable ADC driver for Microchip XEC MCU series. |
|
Enable the driver for Analog Devices ADT7420 High-Accuracy 16-bit Digital I2C Temperature Sensors. |
|
The critical overtemperature pin asserts when the temperature exceeds this value. The default value of 147 is the reset default of the ADT7420. |
|
Specify the temperature hysteresis in °C for the THIGH, TLOW, and TCRIT temperature limits. |
|
Priority of thread used by the driver to handle interrupts. |
|
Stack size of thread used by the driver to handle interrupts. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
Enable driver for ADXL345 Three-Axis Digital Accelerometer. |
|
Enable driver for ADXL362 Three-Axis Digital Accelerometers. |
|
Unsigned value that sets the ADXL362 interrupt mode in either absolute or referenced mode. 0 - Absolute mode 1 - Referenced mode |
|
100 Hz |
|
12.5 Hz |
|
200 Hz |
|
25 Hz |
|
400 Hz |
|
50 Hz |
|
Set at runtime. |
|
2G |
|
4G |
|
8G |
|
Set at runtime. |
|
Unsigned value that the adxl362 samples are compared to in activity trigger mode. |
|
8 bit value written to the activity timer register 0 to 254, seconds is this value div by ODR |
|
Unsigned value that the adxl362 samples are compared to in inactivity trigger mode. |
|
16 bit value written to the activity timer register 0 to 65535, seconds is this value div by ODR |
|
Unsigned value that sets the ADXL362 in different interrupt modes. 0 - Default mode 1 - Linked mode 3 - Loop mode |
|
Priority of thread used by the driver to handle interrupts. |
|
Stack size of thread used by the driver to handle interrupts. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
Enable driver for ADXL372 Three-Axis Digital Accelerometers. |
|
Threshold for activity detection. |
|
The activity timer implements a robust activity detection that minimizes false positive motion triggers. When the timer is used, only sustained motion can trigger activity detection. Number of multiples of 3.3 ms activity timer for which above threshold acceleration is required to detect activity. It is 3.3 ms per code for 6400 Hz ODR, and it is 6.6 ms per code for 3200 Hz ODR and below. |
|
1600 Hz |
|
200 Hz |
|
3200 Hz |
|
400 Hz |
|
800 Hz |
|
ODR/210 |
|
ODR/411 |
|
ODR/812 |
|
ODR/1616 |
|
Disabled |
|
I2C Interface |
|
Threshold for in-activity detection. |
|
The time that all enabled axes must be lower than the inactivity threshold for an inactivity event to be detected. Number of multiples of 26 ms inactivity timer for which below threshold acceleration is required to detect inactivity. It is 26 ms per code for 3200 Hz ODR and below, and it is 13 ms per code for 6400 Hz ODR. |
|
Disabled |
|
In this mode, acceleration data is provided continuously at the output data rate (ODR). |
|
1600 Hz |
|
3200 Hz |
|
400 Hz |
|
6400 Hz |
|
800 Hz |
|
In most high-g applications, a single (3-axis) acceleration sample at the peak of an impact event contains sufficient information about the event, and the full acceleration history is not required. In this mode the device returns only the over threshold Peak Acceleration between two consecutive sample fetches. |
|
Activity detection can be configured as referenced or absolute. When using absolute activity detection, acceleration samples are compared directly to a user set threshold to determine whether motion is present. In many applications, it is advantageous for activity detection to be based not on an absolute threshold, but on a deviation from a reference point or orientation. |
|
SPI Interface |
|
Priority of thread used by the driver to handle interrupts. |
|
Stack size of thread used by the driver to handle interrupts. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
Enable driver for AK8975 magnetometer. |
|
This module implements a kernel device driver for the Altera Avalon Interval Timer as described in the Embedded IP documentation, for use with Nios II and possibly other Altera soft CPUs. It provides the standard “system clock driver” interfaces. |
|
Enable driver for AMG88XX infrared thermopile sensor. |
|
Priority of thread used by the driver to handle interrupts. |
|
Stack size of thread used by the driver to handle interrupts. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
Enable driver for iAQ-core Digital VOC sensor. |
|
Enable the LED strip driver for a chain of APA102 RGB LEDs. These are sold as DotStar by Adafruit and Superled by others. |
|
Enable driver for APDS9960 sensors. |
|
16x |
|
1x |
|
4x |
|
64x |
|
Enable Ambient Light Sense (ALS). |
|
1x |
|
2x |
|
4x |
|
8x |
|
100% |
|
150% |
|
200% |
|
300% |
|
Proximity Pulse Count |
|
16us |
|
32us |
|
4us |
|
8us |
|
Use global thread |
|
No trigger |
|
Use the x86 local APIC as the system time source. |
|
This option specifies the IRQ used by the local APIC timer. |
|
This option specifies the IRQ priority used by the local APIC timer. |
|
If your CPU supports invariant TSC, and you know the ratio of the TSC frequency to CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC (the local APIC timer frequency), then enable this for a much faster and more accurate z_timer_cycle_get_32(). |
|
TSC to local APIC timer frequency divisor (M) |
|
TSC to local APIC timer frequency multiplier (N) |
|
The ARCv2 interrupt unit has 16 allocated exceptions associated with vectors 0 to 15 and 240 interrupts associated with vectors 16 to 255. The interrupt unit is optional in the ARCv2-based processors. When building a processor, you can configure the processor to include an interrupt unit. The ARCv2 interrupt unit is highly programmable. |
|
This module implements a kernel device driver for the ARCv2 processor timer 0 and provides the standard “system clock driver” interfaces. |
|
This option specifies the IRQ priority used by the ARC timer. Lower values have higher priority. |
|
This module implements a kernel device driver for the ARM architected timer which provides per-cpu timers attached to a GIC to deliver its per-processor interrupts via PPIs. |
|
Configure Clock Config Device name |
|
Say Y here if you want Zephyr to communicate with system firmware implementing the PSCI specification for CPU-centric power management operations described in ARM document number ARM DEN 0022A (“Power State Coordination Interface System Software on ARM processors”). |
|
Enable support for Audio |
|
Enable Audio Codec Driver Configuration |
|
Audio codec device driver initialization priority. |
|
Enable Digital Microphone Driver Configuration |
|
Audio Digital Microphone device driver initialization priority. |
|
Enable Intel digital PDM microphone driver |
|
Enable MPXXDTYY microphone support on the selected board |
|
Enable TLV320DAC support on the selected board |
|
Enable driver for BMA280 I2C-based triaxial accelerometer sensor family. |
|
7.81Hz |
|
15.63HZ |
|
31.25Hz |
|
62.5Hz |
|
125Hz |
|
250HZ |
|
500Hz |
|
unfiltered |
|
+/-16g |
|
+/-2g |
|
+/-4g |
|
+/-8g |
|
Priority of thread used by the driver to handle interrupts. |
|
Stack size of thread used by the driver to handle interrupts. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
Enable driver for BMC150 I2C-based magnetometer sensor. |
|
Enhanced regular (15, 27, 10) |
|
High accuracy (47, 83, 20) |
|
Low power (3, 3, 10) |
|
Regular (9, 15, 10) |
|
Enable alteration of sampling rate attribute at runtime. |
|
Enable alteration of XY oversampling at runtime. |
|
Enable alteration of Z oversampling at runtime. |
|
Enable triggers for BMC150 magnetometer |
|
Enable data ready interrupt for BMC150 magnetometer |
|
Specify the internal thread stack size. |
|
Enable driver for BME280 I2C-based or SPI-based temperature and pressure sensor. |
|
16 |
|
2 |
|
4 |
|
8 |
|
filter off |
|
x16 |
|
x1 |
|
x2 |
|
x4 |
|
x8 |
|
forced |
|
normal |
|
x16 |
|
x1 |
|
x2 |
|
x4 |
|
x8 |
|
0.5ms |
|
1000ms |
|
125ms |
|
2000ms BMP280 / 10ms BME280 |
|
250ms |
|
4000ms BMP280 / 20ms BME280 |
|
500ms |
|
62.5ms |
|
x16 |
|
x1 |
|
x2 |
|
x4 |
|
x8 |
|
Enable driver for BME680 I2C-based based temperature, pressure, humidity and gas sensor. |
|
128 |
|
16 |
|
2 |
|
32 |
|
4 |
|
64 |
|
8 |
|
filter off |
|
197 |
|
1943 |
|
320 |
|
400 |
|
x16 |
|
x1 |
|
x2 |
|
x4 |
|
x8 |
|
x16 |
|
x1 |
|
x2 |
|
x4 |
|
x8 |
|
x16 |
|
x1 |
|
x2 |
|
x4 |
|
x8 |
|
Enable Bosch BMG160 gyroscope support. |
|
Fast bus speed of up to 400KHz. |
|
Standard bus speed of up to 100kHz. |
|
100 Hz |
|
1000 Hz |
|
200 Hz |
|
2000 Hz |
|
400 Hz |
|
Set at runtime. |
|
1000 DPS |
|
125 DPS |
|
2000 DPS |
|
250 DPS |
|
500 DPS |
|
Set at runtime. |
|
The priority of the thread used for handling interrupts. |
|
The thread stack size. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
Enable Bosch BMI160 inertial measurement unit that provides acceleration and angular rate measurements. |
|
100 Hz |
|
1600 Hz |
|
200 Hz |
|
25 Hz |
|
1.56 Hz |
|
12.5 Hz |
|
0.78 Hz |
|
6.25 Hz |
|
3.125 Hz |
|
400 Hz |
|
50 Hz |
|
800 Hz |
|
Set at runtime. |
|
low power |
|
normal |
|
Set at runtime. |
|
suspended/not used |
|
16G |
|
2G |
|
4G |
|
8G |
|
Set at runtime. |
|
100 Hz |
|
1600 Hz |
|
200 Hz |
|
25 Hz |
|
3200 Hz |
|
400 Hz |
|
50 Hz |
|
800 Hz |
|
Set at runtime. |
|
fast start-up |
|
normal |
|
Set at runtime. |
|
suspended/not used |
|
1000 DPS |
|
125 DPS |
|
2000 DPS |
|
250 DPS |
|
500 DPS |
|
Set at runtime. |
|
The priority of the thread used for handling interrupts. |
|
The thread stack size. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
Enable driver for BMM150 I2C-based Geomagnetic sensor. |
|
Enhanced regular (15, 27, 10) |
|
High accuracy (47, 83, 20) |
|
Low power (3, 3, 10) |
|
Regular (9, 15, 10) |
|
Enable alteration of sampling rate attribute at runtime. |
|
Enable alteration of XY oversampling at runtime. |
|
Enable alteration of Z oversampling at runtime. |
|
Enable I2C-based driver for BQ274xx Fuel Gauge. |
|
Enable support for devices compatible with the BlueNRG Bluetooth Stack. Current driver supports: ST BLUENRG-MS. |
|
Enable the quirk wherein BT Host stack will auto-initiate Data Length Update procedure for new connections for controllers that do not auto-initiate the procedure if the default data length parameters are not equal to the initial parameters. This has to be enabled when the BLE controller connected is Zephyr open source controller. |
|
Bluetooth H:4 UART driver. Requires hardware flow control lines to be available. |
|
Bluetooth three-wire (H:5) UART driver. Implementation of HCI Three-Wire UART Transport Layer. |
|
This is intended for unit tests where no internal driver should be selected. |
|
Bluetooth HCI driver for communication with another CPU using RPMsg framework. |
|
Enable RPMsg configuration for nRF53. Two channels of the IPM driver are used in the HCI driver: channel 0 for TX and channel 1 for RX. |
|
Supports Bluetooth ICs using SPI as the communication protocol. HCI packets are sent and received as single Byte transfers, prepended after a known header. Headers may vary per device, so additional platform specific knowledge may need to be added as devices are. |
|
Enable support for devices compatible with the BlueNRG Bluetooth Stack. Current driver supports: ST BLUENRG-MS. |
|
BT SPI init priority |
|
TODO |
|
STM32 IPM stack size for RX thread |
|
This option specifies the name of UART device to be used for Bluetooth. |
|
This driver provides access to the local Linux host’s Bluetooth adapter using a User Channel HCI socket to the Linux kernel. It is only intended to be used with the native POSIX build of Zephyr. The Bluetooth adapter must be powered off in order for Zephyr to be able to use it. |
|
Enable CAN Driver Configuration |
|
This option enables the automatic bus-off recovery according to ISO 11898-1 (recovery after 128 occurrences of 11 consecutive recessive bits). When this option is enabled, the recovery API is not available. |
|
Enable CAN-FD compatible API |
|
CAN device driver initialization priority. Do not mess with it unless you know what you are doing. Note that the priority needs to be lower than the net stack so that it can start before the networking sub-system. |
|
This is a dummy driver that can only loopback messages. |
|
“Device name for the loopback device” |
|
Number of TX frames that can be buffered. The send functions puts frame int this queue and TX thread takes the messages from this msgq and calls the respective receiver if the filter matches. |
|
Priority of the TX thread. The TX thread calls the callbacks of the receiver if the filter matches. |
|
Stack size of the TX thread. The TX thread calls the callbacks of the receiver if the filter matches. |
|
Defines the array size of the callback/msgq pointers. Must be at least the size of concurrent reads. |
|
Enable MCP2515 CAN Driver |
|
MCP2515 driver initialization priority, must be higher than SPI. |
|
Priority level of the internal thread which is ran for interrupt handling and incoming packets. |
|
Size of the stack used for internal thread which is ran for interrupt handling and incoming packets. |
|
Enable support for mcux flexcan driver. |
|
Enable IPv6 Networking over can (6loCAN) |
|
CAN NET device driver initialization priority. Do not mess with it unless you know what you are doing. Note that the priority needs to be lower than the net stack so that it can start before the networking sub-system. |
|
Name of the network device driver for IPv6 over CAN. |
|
This option enables a timestamp value of the CAN free running timer. The value is incremented every bit time and starts when the controller is initialized. |
|
Enable CAN Shell for testing. |
|
Enable STM32 CAN Driver. Tested on stm32F0, stm32L4 and stm32F7 series. |
|
Number of frames in the buffer of a zcan_work. |
|
These are 4 in number supporting a max of 32 interrupts each. |
|
Parent interrupt number to which CAVS_0 maps |
|
Parent interrupt number to which CAVS_1 maps |
|
Parent interrupt number to which CAVS_2 maps |
|
Parent interrupt number to which CAVS_3 maps |
|
Cavs Interrupt Logic initialization priority. |
|
This indicates the offset in the SW_ISR_TABLE beginning from where the ISRs for CAVS Interrupt Controller are assigned. |
|
The DSP wall clock timer is a timer driven directly by external oscillator and is external to the CPU core(s). It is not as fast as the internal core clock, but provides a common and synchronized counter for all CPU cores (which is useful for SMP). |
|
This module implements a kernel device driver for the TI SimpleLink CC13X2_CC26X2 series Real Time Counter and provides the standard “system clock driver” interfaces. |
|
Enable driver for CCS811 Gas sensors. |
|
Measurements disabled |
|
Measurement every second |
|
Measurement every ten seconds |
|
Measurement every sixty seconds |
|
Measurement every 250 milliseconds |
|
Priority of thread used by the driver to handle interrupts. |
|
Stack size of thread used by the driver to handle interrupts. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
Do a margin check flash command before reading an area. This feature prevents erroneous/forbidden reading. Some ECC enabled devices will crash when reading an erased or wrongly programmed area. |
|
Enable support for hardware clock controller. Such hardware can provide clock for other subsystem, and thus can be also used for power efficiency by controlling their clock. Note that this has nothing to do with RTC. |
|
Enable driver for Reset & Clock Control subsystem found in STM32F4 family of MCUs |
|
This option controls the priority of clock control device initialization. Higher priority ensures that the device is initialized earlier in the startup cycle. If unsure, leave at default value 1 |
|
Enable PLL on Beetle. Select n if not sure. |
|
Enable support for ESP32 clock driver. |
|
This option enables LiteX clock control driver. It gives ability to change clock parameters such as phase, duty cycle, frequency for up to 7 clock outputs |
|
Enable driver for reset and clock control used in LPC11U6X MCUs |
|
Enable SRAM1 |
|
Enable USB RAM |
|
Use the internal oscillator as the clock source for the PLL |
|
Use the system oscillator as the clock source for the PLL |
|
Enable support for mcux ccm driver. |
|
Enable support for mcux mcg driver. |
|
Enable support for MCUX PCC driver. |
|
Enable support for mcux scg driver. |
|
Enable support for mcux sim driver. |
|
Enable support for mcux clock driver. |
|
Enable support for NPCX clock controller driver. |
|
Enable support for the Nordic Semiconductor nRFxx series SoC clock driver. |
|
Enables retrieving debug information like number of performed or skipped calibrations. |
|
If RTC is used as system timer then LF clock is always on and handling can be simplified. |
|
Calibration is skipped when temperature change since last calibration was less than configured threshold. If number of consecutive skips reaches configured value then calibration is performed unconditionally. Set to 0 to perform calibration periodically regardless of temperature change. |
|
Periodically, calibration action is performed. Action includes temperature measurement followed by clock calibration. Calibration may be skipped if temperature change (compared to measurement of previous calibration) did not exceeded CLOCK_CONTROL_NRF_CALIBRATION_TEMP_DIFF and number of consecutive skips did not exceeded CLOCK_CONTROL_NRF_CALIBRATION_MAX_SKIP. |
|
Calibration is triggered if the temperature has changed by at least this amount since the last calibration. |
|
This option can be enabled to force an alternative implementation of the clock control driver. |
|
76 ppm to 100 ppm |
|
101 ppm to 150 ppm |
|
0 ppm to 20 ppm |
|
151 ppm to 250 ppm |
|
21 ppm to 30 ppm |
|
251 ppm to 500 ppm |
|
31 ppm to 50 ppm |
|
51 ppm to 75 ppm |
|
External full swing |
|
External low swing |
|
RC Oscillator |
|
If calibration is disabled when RC is used for low frequency clock then accuracy of the low frequency clock will degrade. Disable on your own risk. |
|
Synthesized from HFCLK |
|
Crystal Oscillator |
|
Shell commands |
|
Enable support for RV32M1 PCC driver. |
|
Enable driver for Reset & Clock Control subsystem found in STM32 family of MCUs |
|
This option controls the priority of clock control device initialization. Higher priority ensures that the device is initialized earlier in the startup cycle. If unsure, leave at default value 1 |
|
APB1 prescaler, allowed values: From 1 to 10. |
|
APB2 prescaler, allowed values: From 1 to 10. |
|
APB3 prescaler, allowed values: From 1 to 10. |
|
Core Domain Clock Generator PLL frequency, allowed values: From 10Mhz to 100Mhz. |
|
HCLK4 prescaler, allowed values: 1, 2, 4, 8, 16, 64, 128, 256, 512. |
|
AHB prescaler, allowed values: 1, 2, 4, 8, 16, 64, 128, 256, 512. |
|
APB1 Low speed clock (PCLK1) prescaler, allowed values: 1, 2, 4, 8, 16 |
|
APB2 High speed clock (PCLK2) prescaler, allowed values: 1, 2, 4, 8, 16 |
|
CPU1 HCLK prescaler, allowed values: 1, 2, 4, 8, 16, 64, 128, 256, 512. |
|
CPU2 HCLK prescaler, allowed values: 1, 2, 4, 8, 16, 64, 128, 256, 512. |
|
D1 Domain, CPU1 clock (sys_d1cpre_ck prescaler), allowed values: 1, 2, 4, 8, 16, 64, 128, 256, 512. |
|
APB3 clock (rcc_pclk3) prescaler, allowed values: 1, 2, 4, 8, 16 |
|
APB1 clock (rcc_pclk1) prescaler, allowed values: 1, 2, 4, 8, 16 |
|
APB2 clock (rcc_pclk2) prescaler, allowed values: 1, 2, 4, 8, 16 |
|
APB4 clock (rcc_pclk4) prescaler, allowed values: 1, 2, 4, 8, 16 |
|
hclk prescaler, allowed values: 1, 2, 4, 8, 16, 64, 128, 256, 512. |
|
Enable this option to bypass external high-speed clock (HSE). |
|
Value of external high-speed clock (HSE). |
|
HSI Divisor to divide HSI base frequency value allowed values: 1, 2, 4, 8 |
|
Enable the low-speed external (LSE) clock supplied with a 32.768 kHz crystal resonator oscillator. |
|
allowed values: 1, 2, 3, 4, 5 |
|
Use HSE as source of MCO1 |
|
Use HSI as source of MCO1 |
|
Use LSE as source of MCO1 |
|
MCO1 output disabled, no clock on MCO1 |
|
Use PLLCLK as source of MCO1 |
|
allowed values: 1, 2, 3, 4, 5 |
|
Use HSE as source of MCO2 |
|
MCO2 output disabled, no clock on MCO2 |
|
Use PLLCLK as source of MCO2 |
|
Use PLLI2S as source of MCO2 |
|
Use SYSCLK as source of MCO2 |
|
Enable hardware auto-calibration with LSE. |
|
Frequency range of MSI when MSI range is provided in RCC_CR register Range 0: 100kHz Range 1: 200kHz Range 2 around 400 kHz Range 3 around 800 kHz Range 4: 1 MHz Range 5: 2 MHz Range 6: 4 MHz (reset value) Range 7: 8 MHz Range 8: 16 MHz Range 9: 24 MHz Range 10: 32 MHz Range 11: 48 MHz |
|
Enable PLL3. It is used to generate the kernel clock for some peripherals. |
|
PLL divisor, allowed values: 1-63. |
|
PLL3 multiplier, allowed values: 4-512. |
|
PLL3 P Output divisor, allowed values: 1-128. |
|
Enable PLL3 P output. |
|
PLL3 Q Output divisor, allowed values: 1-128. |
|
Enable PLL3 Q output. |
|
PLL3 R Output divisor, allowed values: 1-128. |
|
Enable PLL3 R output. |
|
PLL divisor, allowed values: 2-4. |
|
PLL multiplier, allowed values: 2-16. PLL output must not exceed 48MHz for STM32F0 series or 72MHz for STM32F3 series. |
|
PLLM division factor needs to be set correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit PLL jitter. Allowed values: 2-63 |
|
PLLN multiplier factor needs to be set correctly to ensure that the VCO output frequency is between 100 and 432 MHz, except on STM32F401 where the frequency must be between 192 and 432 MHz. Allowed values: 50-432 (STM32F401: 192-432) |
|
PREDIV is a PLL clock signal prescaler for the HSE output. It is supported by those parts that do not support PREDIV1. If configured on a non-supported part, this config will be ignored. Allowed values: 1 - 16. |
|
PREDIV1 is a PLL clock signal prescaler for any PLL input. It is supported by STM32F04xx, STM32F07xx, STM32F09xx, STM32F030xC, STM32F302xE, STM32F303xE and STM32F39xx parts. If configured on a non-supported part, this config will be ignored. Allowed values: 1 - 16. |
|
PLLP division factor needs to be set correctly to not exceed 84MHz. Allowed values: 2, 4, 6, 8 |
|
The USB OTG FS requires a 48MHz clock to work correctly. SDIO and RNG need a frequency lower than or equal to 48 MHz to work correctly. Allowed values: 2-15 |
|
PLL R Output divisor, allowed values: 1-128. |
|
Use CSI 4MHz as source of the main PLL. |
|
Use HSE as source of PLL |
|
Use HSI as source of PLL |
|
Use MSI as source of PLL |
|
Use PLL2 as source of main PLL. This is equivalent of defining PLL2 as source PREDIV1SCR. If not selected, default source is HSE. |
|
Use CSI as source of SYSCLK |
|
Use HSE as source of SYSCLK |
|
Use HSI as source of SYSCLK |
|
Use MSI as source of SYSCLK |
|
Use PLL as source of SYSCLK |
|
Console drivers |
|
This option enables console input handler allowing to write simple interaction between serial console and the OS. |
|
This is an option to be enabled by console drivers to signal that some kind of console exists. |
|
This option can be used to modify the maximum length a console input can be. |
|
This module implements a kernel device driver for the Cortex-M processor SYSTICK timer and provides the standard “system clock driver” interfaces. |
|
Enable support for counter and timer. |
|
Counter driver for x86 CMOS/RTC clock |
|
Enable counter driver based on RTCC module for Silicon Labs Gecko chips. |
|
Enable the IMX EPIT driver. |
|
Enable counter driver based on Maxim DS3231 I2C device. |
|
DS3231 device driver initialization priority. |
|
Enable support for mcux General Purpose Timer (GPT) driver. |
|
Enable support for the MCUX Low Power Timer (LPTMR). |
|
Enable support for the MCUX Periodic Interrupt Timer (PIT). |
|
Enable support for mcux rtc driver. |
|
Enable counter on COUNTER_0 |
|
native_posix counter frequency in Hz |
|
Enable Counter on RTC0 |
|
Enable Counter on RTC1 |
|
Enable Counter on RTC2 |
|
Build RTC driver for STM32 SoCs. Tested on STM32 F0, F2, F3, F4, L1, L4, F7, G0, G4, H7 series |
|
Force a backup domain reset on startup |
|
Use LSE as RTC clock |
|
Use LSI as RTC clock |
|
Enable LSE bypass |
|
Xtal mode higher driving capability |
|
Xtal mode lower driving capability |
|
Xtal mode medium high driving capability |
|
Xtal mode medium low driving capability |
|
Enable the SAM0 series timer counter (TC) driver in 32-bit wide mode. |
|
Enable Counter on TIMER0 |
|
Enable Counter on TIMER1 |
|
Enable Counter on TIMER2 |
|
Enable Counter on TIMER3 |
|
Enable Counter on TIMER4 |
|
Enable counter driver for Microchip XEC MCU series. Such driver will expose the basic timer devices present on the MCU. |
|
Enable counter support for the Xilinx AXI Timer v2.0 IP. |
|
Crypto Drivers [EXPERIMENTAL] |
|
Enable Atmel ATAES132A 32k AES Serial EEPROM support. |
|
Name for the ATAES132A driver which will be used for binding. |
|
ATAES132A chip’s I2C address. |
|
Master I2C port name through which ATAES132A chip is accessed. |
|
Fast bus speed of up to 400KHz. |
|
Standard bis speed of up to 100KHz. |
|
Crypto devices initialization priority. |
|
Enable mbedTLS shim layer compliant with crypto APIs. You will need to fill in a relevant value to CONFIG_MBEDTLS_HEAP_SIZE. |
|
Device name for mbedTLS Pseudo device. |
|
This can be used to tweak the amount of sessions the driver can handle in parallel. |
|
Enable nRF HAL-based AES ECB encryption driver |
|
Enable STM32 HAL-based Cryptographic Accelerator driver. |
|
This can be used to tweak the amount of sessions the driver can handle in parallel. |
|
Enable TinyCrypt shim layer compliant with crypto APIs. |
|
Device name for TinyCrypt Pseudo device. |
|
This can be used to tweak the amount of sessions the driver can handle in parallel. |
|
Enable DAC (Digital to Analog Converter) driver configuration. |
|
Enable the driver for the TI DACx0508. |
|
DACx0508 DAC device driver initialization priority. |
|
Enable the driver for the TI DACX3608. |
|
DACX3608 DAC device driver initialization priority. |
|
Enable the driver for the NXP Kinetis MCUX DAC. |
|
Enable the driver for the NXP Kinetis MCUX DAC32. |
|
Enable the DAC test output. |
|
Enables the Atmel SAM0 MCU Family Digital-to-Analog (DAC) driver. |
|
Enable DAC related shell commands. |
|
Enable the driver implementation for the stm32xx DAC |
|
Enable driver for the DHT temperature and humidity sensor family. |
|
Enable display drivers |
|
Enable support for mcux eLCDIF driver. |
|
DMA driver Configuration |
|
Enable DMAMUX support. |
|
IRQ Priority for the DMA Controller. |
|
Device name for DMA Controller 0. |
|
Device name for DMA Controller 1. |
|
Device name for DMA Controller 2. |
|
When this option is true, 64 bit source and dest DMA addresses are supported. |
|
DesignWare DMA driver. |
|
Broadcom PAX(PCIE<->AXI) DMA driver |
|
Add paranoid checks for buffer address/size alignments for each dma packet. |
|
PAX DMA hardware ring operation in doorbell mode |
|
PAX DMA API blocks until dma completion alert is signalled from ring interrupt handler. |
|
PAX DMA API polls for dma completions |
|
PAX DMA hardware ring operation in toggle mode |
|
Broadcom PAX(PCIE<->AXI) DMA driver version 2 |
|
number of transfer descriptors in a queue for SG mode |
|
DMA driver for MCUX series SoCs. |
|
DMA driver for MCUX LPC MCUs. |
|
test slot start num |
|
Enable Nios-II Modular Scatter-Gather DMA(MSGDMA) driver. |
|
This option enables support of pl330 DMA Controller. |
|
DMA driver for Atmel SAM0 series MCUs. |
|
Enable Atmel SAM MCU Family Direct Memory Access (XDMAC) driver. |
|
DMA driver for STM32 series SoCs. |
|
Enable shared IRQ support on devices where channels share 1 IRQ. |
|
Enable DMA V1 support. |
|
Enable DMA V2 support. |
|
number of TCD in a queue for SG mode |
|
Enable driver for DPS310 I2C-based temperature and pressure sensor. |
|
x128 |
|
x16 |
|
x1 |
|
x2 |
|
x32 |
|
x4 |
|
x64 |
|
x8 |
|
x128 |
|
x16 |
|
x1 |
|
x2 |
|
x32 |
|
x4 |
|
x64 |
|
x8 |
|
Add support for KSZ8794 DSA device driver. |
|
Add support for tail tagging on KSZ8794 DSA device. |
|
Enable dummy display driver compliant with display driver API. |
|
Dummy display device name |
|
X resolution for dummy display |
|
Y resolution for dummy display |
|
Designware Interrupt Controller can be used as a 2nd level interrupt controller which combines several sources of interrupt into one line that is then routed to the 1st level interrupt controller. |
|
DesignWare Interrupt Controller initialization priority. |
|
Give a name for the instance of Designware Interrupt Controller |
|
Parent interrupt number to which DW_ICTL maps |
|
This indicates the offset in the SW_ISR_TABLE beginning from where the ISRs for Designware Interrupt Controller are assigned. |
|
Enable the embedded controller host command peripheral driver. This is needed by the EC host command framework to send and receive data on the appropriate EC host bus. |
|
Enable the EC host command simulator. |
|
Enable Error Detection and Correction (EDAC) driver. |
|
Enable Error injection capability for test error checking and reporting. Should not be enabled in production system. |
|
This option selects In-Band ECC (IBECC) IP support. |
|
Enable EDAC shell for debugging EDAC. |
|
Enable support for EEPROM hardware. |
|
Enable support for Atmel AT24 (and compatible) I2C EEPROMs. |
|
Enable support for Atmel AT25 (and compatible) SPI EEPROMs. |
|
Enable support for Atmel AT2x (and compatible) I2C/SPI EEPROMs. |
|
AT2X EEPROM init priority |
|
Enable support for the on-chip EEPROM found on NXP LPC11U6x MCUs. |
|
Enable the EEPROM shell with EEPROM related commands. |
|
Size of the buffer used for EEPROM read/write commands in the EEPROM shell. |
|
Enable Simulated EEPROM driver. |
|
Minimum read time (µS) |
|
Minimum write time (µS) |
|
Enable Simulated hardware timing. |
|
Enable EEPROM support on the STM32 L0, L1 family of processors. |
|
Enable driver for ENS210 Digital Temperature and Humidity sensor. |
|
Check the crc value after data reading. |
|
Enable relative humidity measurements in continuous mode |
|
Disable relative humidity measurements |
|
Enable relative humidity measurements in single shot mode |
|
Number of retries when value reading failed, value not valid or crc not ok. |
|
Number of retries when status reading failed or device not ready. |
|
Enable temperature measurements in continuous mode |
|
Disable temperature measurements |
|
Enable temperature measurements in single shot mode |
|
The number of samples detected with repeating patterns before an alarm event is triggered. The associated FRO is automatically shut down. |
|
The size in bytes of the buffer used to store entropy generated by the hardware. Should be a power of two for high performance. |
|
This option enables the driver for the True Random Number Generator (TRNG) for TI SimpleLink CC13xx / CC26xx SoCs. |
|
The number of samples used to generate entropy. The time required to generate 64 bits of entropy is determined by the number of FROs enabled, the sampling (system) clock frequency, and this value. |
|
The number of FROs allowed to be shutdown before the driver attempts to take corrective action. |
|
This option enables the entropy number generator for ESP32 SoCs. With Wi-Fi and Bluetooth disabled, this will produce pseudo-entropy numbers: noise from these radios are used to feed entropy in this generator. |
|
This option enables the true random number generator driver based on the TRNG. |
|
Include entropy drivers in system config. |
|
This is an option to be enabled by individual entropy driver to signal that there is a true entropy driver. |
|
This option enables the RNG module, which is an entropy number generator, based on Pseudo-Random Binary Sequences (PRBS) for LiteX SoC builder |
|
This option enables the true random number generator (TRNG) driver based on the MCUX RNG driver on LPC Family. |
|
This option enables the random number generator accelerator (RNGA) driver based on the MCUX RNGA driver. |
|
This option enables the true random number generator (TRNG) driver based on the MCUX TRNG driver. |
|
This option enables the RNG bias correction, which guarantees a uniform distribution of 0 and 1. When this option is enabled, the time to generate a byte cannot be guaranteed. |
|
Buffer length in bytes used to store entropy bytes generated by the hardware to make them ready for ISR consumers. Please note, that size of the pool must be a power of 2. |
|
Low water-mark threshold in bytes to trigger entropy generation for ISR consumers. As soon as the number of available bytes in the buffer goes below this number hardware entropy generation will be started. |
|
This option enables the RNG peripheral, which is a random number generator, based on internal thermal noise, that provides a random 8-bit value to the host when read. |
|
Buffer length in bytes used to store entropy bytes generated by the hardware to make them ready for thread mode consumers. Please note, that size of the pool must be a power of 2. |
|
Low water-mark threshold in bytes to trigger entropy generation for thread mode consumers. As soon as the number of available bytes in the buffer goes below this number hardware entropy generation will be started. |
|
This option can be enabled to force an alternative implementation of the entropy driver. |
|
This option enables the true random number generator (TRNG) driver based on the RV32M1 TRNG driver. |
|
Enable True Random Number Generator (TRNG) driver for Atmel SAM MCUs. |
|
Buffer length in bytes used to store entropy bytes generated by the hardware to make them ready for ISR consumers. Please note, that size of the pool must be a power of 2. |
|
Low water-mark threshold in bytes to trigger entropy generation for ISR consumers. As soon as the number of available bytes in the buffer goes below this number hardware entropy generation will be started. |
|
This option enables the RNG processor, which is a entropy number generator, based on a continuous analog noise, that provides a entropy 32-bit value to the host when read. It is available for F4 (except STM32F401 & STM32F411), L4, F7, H7 and G4 series. |
|
Buffer length in bytes used to store entropy bytes generated by the hardware to make them ready for thread mode consumers. Please note, that size of the pool must be a power of 2. |
|
Low water-mark threshold in bytes to trigger entropy generation for thread mode consumers. As soon as the number of available bytes in the buffer goes below this number hardware entropy generation will be started. |
|
Enable ESPI Driver. |
|
Enable automatic acknowledge of slave basic configuration been completed by sending a virtual wire message to the eSPI master. This depends on SPI boot configuration. It could be either very early in the flow after the VW channel is configured. Or it could be until flash channel is configured. |
|
Enable automatic acknowledge from eSPI slave towards eSPI host whenever it receives suspend or reset warning. If this is disabled, it means the app wants to be give the opportunity to prepare for either HOST suspend or reset. |
|
Enable the eSPI emulator driver. This is a fake driver, it does not talk to real hardware. Instead it talks to emulation drivers that pretend to be devices on the emulated eSPI bus. It is used for testing drivers for eSPI devices. eSPI is an interface using SPI wires, whose main goal is to reduce the number of required pins. It includes the functionality of LPC, SMB, SPI itself (flash access) and GPIO (virtual wires). Please refer to the specification for more details (it is good for the introduction as well) https://www.intel.com/content/dam/support/us/en/documents/software/chipset-software/327432-004_espi_base_specification_rev1.0_cb.pdf |
|
eSPI Controller supports flash channel. |
|
Driver initialization priority for eSPI driver. |
|
Enable support for NPCX ESPI driver. The Intel Enhanced Serial Peripheral Interface (eSPI) provides a path for migrating host sub-devices via LPC to a lower pin count, higher bandwidth bus. So far, this driver supports all of functionalities beside flash channel support. It will be supported in the future. Please refer https://www.intel.com/content/www/us/en/support/articles/000020952/ software/chipset-software.html for more detail. |
|
This is the port size used by the Host and EC to communicate over the shared memory region to return the ACPI response data. Please notice the valid value in npcx ec series for this option is 8/16/32/ 64/128/256/512/1024/2048/4096 bytes. |
|
This is the port size used by the Host and EC to communicate over the shared memory region to return the host command parameter data. Please notice the valid value in npcx ec series for this option is 8/16/32/64/128/256/512/1024/2048/4096 bytes. |
|
eSPI Controller supports OOB channel. |
|
Enables 8042 keyboard controller over eSPI peripheral channel. |
|
Enables shared memory region over eSPI peripheral channel to access the ACPI response data. |
|
This is the port number used by the Host and EC to communicate over the shared memory region to access the ACPI response data. Please ensure the Host code is configured to use for accessing ACPI response data. Also, ensure the port number selected doesn’t clash with the existing ports. |
|
eSPI Controller supports peripheral channel. |
|
Enables opcode is customized for certain platforms such as Chromebook and so on over eSPI peripheral channel. |
|
Enables debug Port 80 over eSPI peripheral channel. |
|
Enables Embedded Controller (EC) host command subsystem via eSPI peripheral channel. |
|
This is the port number used by the Host and EC to communicate over the eSPI peripheral channel to send EC host command data and its result. Please ensure the Host code is configured to use for accessing host command data and result. Also, ensure the port number selected doesn’t clash with the existing ports. |
|
This is the port number used by the Host and EC to communicate over the eSPI peripheral channel to access the host command request and response data. Please ensure the Host code is configured to use for accessing these package data. Also, ensure the port number selected doesn’t clash with the existing ports. |
|
Enables ACPI Host I/O over eSPI peripheral channel. |
|
Enables ACPI Host I/O over eSPI peripheral channel for private channel. |
|
This is the port number used by the Host and EC to communicate over the private channel. Please ensure the Host code is configured to use the same port. Also, ensure the port number selected doesn’t clash with the existing ports (like 80, 92, 62 etc). |
|
Enables UART over eSPI peripheral channel. |
|
This tells the driver to which SoC UART to direct the UART traffic send over eSPI from host. |
|
Enables eSPI driver in slave mode. |
|
eSPI Controller supports virtual wires channel. |
|
Enable the Microchip XEC ESPI driver. |
|
Enable Intel(R) PRO/1000 Gigabit Ethernet driver. |
|
Enabling this will turn on the hexdump of the received and sent frames. Do not leave on for production. |
|
ENC28J60C Stand-Alone Ethernet Controller with SPI Interface |
|
Include port 0 driver |
|
Enable Full Duplex. Device is configured half duplex when disabled. |
|
Priority level for internal thread which is ran for incoming packet processing. |
|
Size of the stack used for internal thread which is ran for incoming packet processing. |
|
Given timeout in milliseconds. Maximum amount of time that the driver will wait from the IP stack to get a memory buffer before the Ethernet frame is dropped. |
|
ENC424J600C Stand-Alone Ethernet Controller with SPI Interface |
|
Priority level for internal thread which is ran for incoming packet processing. |
|
Size of the stack used for internal thread which is ran for incoming packet processing. |
|
Given timeout in milliseconds. Maximum amount of time that the driver will wait from the IP stack to get a memory buffer before the Ethernet frame is dropped. |
|
Enable Ethernet driver for Silicon Labs Gecko chips. |
|
Set the RX idle timeout period in milliseconds after which the PHY’s carrier status is re-evaluated. |
|
IRQ priority of Ethernet device |
|
RX thread priority |
|
RX thread stack size |
|
Ethernet device driver initialization priority. Do not mess with it unless you know what you are doing. Note that the priority needs to be lower than the net stack so that it can start before the networking sub-system. |
|
LiteEth Ethernet core driver |
|
LiteEth Ethernet port 0 |
|
IRQ priority |
|
Enable MCUX Ethernet driver. Note, this driver performs one shot PHY setup. There is no support for PHY disconnect, reconnect or configuration change. |
|
Enable hardware acceleration for the following: - IPv4, UDP and TCP checksum (both Rx and Tx) |
|
Some PHY devices, with DSA capabilities do not use SMI for communication with MAC ENET controller. Other busses - like SPI or I2C are used instead. |
|
Enable additional PHY related debug information related to PHY status polling. |
|
Set the PHY status polling period. |
|
Place the Ethernet receiver in promiscuous mode. This may be useful for debugging and not needed for normal work. |
|
Set the frequency in Hz sourced to the PTP timer. If the value is set properly, the timer will be accurate. |
|
Setting this option will configure MCUX clock block to feed RMII reference clock from external source (ENET_1588_CLKIN) |
|
Set the number of RX buffers provided to the MCUX driver. |
|
Set the number of TX buffers provided to the MCUX driver. |
|
Enable native posix ethernet driver. Note, this driver is run inside a process in your host system. |
|
This option sets the TUN/TAP device name in your host system. |
|
This option sets the driver name and name of the network interface in your host system. If there are multiple network interfaces defined, then this value is used as a prefix and the interface names will be zeth0, zeth1, etc. |
|
By default only one network interface is created. It is possible to create multiple interfaces in certain use cases. For example if multiple ports are defined in gPTP, then multiple network interfaces must be created here. |
|
Specify a MAC address for the ethernet interface in the form of six hex 8-bit chars separated by colons (e.g.: aa:33:cc:22:e2:c0). The default is an empty string, which means the code will make 00:00:5E:00:53:XX, where XX will be random. |
|
Enable PTP clock support. |
|
Generate a random MAC address dynamically. |
|
This option sets the name of the script that is run when the host TAP network interface is created. The script should setup IP addresses etc. for the host TAP network interface. The default script accepts following options: -i|–interface <network interface name>, default is zeth -f|–file <config file name>, default is net_setup_host.conf If needed, you can add these options to this script name option. Note that the driver will add -i option with the value of CONFIG_ETH_NATIVE_POSIX_DRV_NAME option to the end of the options list when calling the host setup script. |
|
If set, the native_posix ethernet driver will set up the network
interface, requiring |
|
This option sets the name of the script that is run when the host TAP network interface is created and setup script has been run. The startup script could launch e.g., wireshark to capture the network traffic for the freshly started network interface. Note that the network interface name CONFIG_ETH_NATIVE_POSIX_DRV_NAME is appended at the end of this startup script name. Example script for starting wireshark is provided in ${ZEPHYR_BASE}/samples/net/eth_native_posix/net_start_wireshark.sh file. |
|
By default the startup script is run as a root user. Set here the username to run the script if running it as a root user is not desired. Note that this setting is only for startup script and not for the setup script. The setup script needs to be run always as a root user. |
|
Native posix ethernet driver will strip of VLAN tag from Rx Ethernet frames and sets tag information in net packet metadata. |
|
Tells what Qemu network model to use. This value is given as a parameter to -nic qemu command line option. |
|
Extra arguments passed to QEMU -nic option when Ethernet Networking is enabled. Typically this is used to set the network MAC address of Zephyr instance. This option can contain multiple QEMU option arguments. Each QEMU argument must be separated by comma “,” and no spaces between arguments. Example: “mac=02:03:04:f0:0d:01” or “mac=02:03:04:f0:0d:01,downscript=no” |
|
The network interface name for QEMU. This value is given as a parameter to -nic qemu command line option. The network interface must be created before starting QEMU. The net-setup.sh script from net-tools project can be used to create the network interface. |
|
Enable Atmel SAM MCU Family Ethernet driver. |
|
Number of network buffers that will be permanently allocated by the Ethernet driver. These buffers are used in receive path. They are preallocated by the driver and made available to the GMAC module to be filled in with incoming data. Their number has to be large enough to fit at least one complete Ethernet frame. SAM ETH driver will always allocate that amount of buffers for itself thus reducing the NET_BUF_RX_COUNT which is a total amount of RX data buffers used by the whole networking stack. One has to ensure that NET_PKT_RX_COUNT is large enough to fit at least two Ethernet frames: one being received by the GMAC module and the other being processed by the higher layer networking stack. |
|
Which queue to force the routing to. This affects both the TX and RX queues setup. |
|
This option is meant to be used only for debugging. Use it to force all traffic to be routed through a specific hardware queue. With this enabled it is easier to verify whether the chosen hardware queue actually works. This works only if there are four or fewer RX traffic classes enabled, as the SAM GMAC hardware supports screening up to four traffic classes. |
|
Device name, e.g. I2C_0, of an I2C bus driver device. It is required to obtain handle to the I2C device object. |
|
Read MAC address from an I2C EEPROM. |
|
Internal address of the EEPROM chip where the MAC address is stored. Chips with 1 to 4 byte internal address size are supported. Address size has to be configured in a separate Kconfig option. |
|
Size (in bytes) of the internal EEPROM address. |
|
I2C 7-bit address of the EEPROM chip. |
|
Monitor task execution period in milliseconds. The monitor task is periodically executed to detect and report any changes in the PHY link status to the operating system. |
|
GMAC PHY Address as used by IEEE 802.3, Section 2 MII compatible PHY transceivers. If you have a single PHY on board it is safe to leave it at 0 which is the broadcast address. |
|
Select the number of hardware queues used by the driver. Packets will be routed to appropriate queues based on their priority. |
|
Enable driver for SMSC/LAN911x/9220 family of chips. |
|
Stellaris on-board Ethernet Controller |
|
Set the RX idle timeout period in milliseconds after which the PHY’s carrier status is re-evaluated. |
|
Enable STM32 HAL based Ethernet driver. It is available for all Ethernet enabled variants of the F2, F4, F7 and H7 series. |
|
IRQ priority |
|
This is the byte 3 of the MAC address. |
|
This is the byte 4 of the MAC address. |
|
This is the byte 5 of the MAC address. |
|
Use the MII physical interface instead of RMII. |
|
The phy address to use. |
|
Generate a random MAC address dynamically. |
|
RX thread priority |
|
RX thread stack size |
|
When this option is activated, the buffers for DMA transfer are moved from SRAM to the DTCM (Data Tightly Coupled Memory). |
|
W5500 Stand-Alone Ethernet Controller with SPI Interface |
|
Priority level for internal thread which is ran for incoming packet processing. |
|
Size of the stack used for internal thread which is ran for incoming packet processing. |
|
Given timeout in milliseconds. Maximum amount of time that the driver will wait from the IP stack to get a memory buffer before the Ethernet frame is dropped. |
|
Enable EXTI driver for STM32 line of MCUs |
|
IRQ priority of EXTI0 interrupt |
|
IRQ priority of EXTI10 interrupt |
|
IRQ priority of EXTI11 interrupt |
|
IRQ priority of EXTI12 interrupt |
|
IRQ priority of EXTI13 interrupt |
|
IRQ priority of EXTI14 interrupt |
|
IRQ priority of EXTI15:10 interrupt |
|
IRQ priority of EXTI15:4 interrupt |
|
IRQ priority of EXTI15 interrupt |
|
IRQ priority of EXTI1:0 interrupt |
|
IRQ priority of EXTI1 interrupt |
|
IRQ priority of EXTI2 interrupt |
|
IRQ priority of EXTI3:2 interrupt |
|
IRQ priority of EXTI3 interrupt |
|
IRQ priority of EXTI4 interrupt |
|
IRQ priority of EXTI5 interrupt |
|
IRQ priority of EXTI6 interrupt |
|
IRQ priority of EXTI7 interrupt |
|
IRQ priority of EXTI8 interrupt |
|
IRQ priority of EXTI9:5 interrupt |
|
IRQ priority of EXTI9 interrupt |
|
IRQ priority of LPTIM1 interrupt |
|
IRQ priority of USB OTG FS Wake interrupt |
|
IRQ priority of RVD Through interrupt |
|
IRQ priority of RTC Wake Up interrupt |
|
IRQ priority of Tamper and Timestamp interrupt |
|
This option enables the test random number generator for the native_posix board (ARCH_POSIX). This is based on the host random() API. Note that this entropy generator is only meant for test purposes and does not generate real entropy. It actually generates always the same sequence of random numbers if initialized with the same seed. |
|
Enable support for the flash hardware. |
|
This option is enabled when any flash driver is enabled. |
|
This option is enabled when the SoC flash driver supports retrieving the layout of flash memory pages. |
|
Selected by drivers that support JESD216-compatible flash devices to enable building a common support module. |
|
This option extends the Zephyr flash API with the ability to access the Serial Flash Discoverable Parameter section allowing runtime determination of serial flash parameters for flash drivers that expose this capability. |
|
MCUX FlexSPI NOR driver |
|
This option can be enabled to force an alternative implementation of the flash driver. |
|
Enables API for retrieving the layout of flash memory pages. |
|
Enable the flash shell with flash related commands such as test, write, read and erase. |
|
Enable the flash simulator. |
|
If selected, writing to a non-erased program unit will succeed, otherwise, it will return an error. Keep in mind that write operations can only pull bits to zero, regardless. |
|
If selected, turning on write protection will also prevent erasing. |
|
Minimum erase time (µS) |
|
Minimum read time (µS) |
|
Minimum write time (µS) |
|
Enable hardware timing simulation |
|
Only up to this number of beginning pages will be tracked while catching dedicated flash operations and thresholds. This number is not automatic because implementation uses UNTIL_REPEAT() macro, which is limited to take explicitly number of iterations. This is why it’s not possible to calculate the number of pages with preprocessor using DT properties. |
|
If selected, the reading operation does not check if access is aligned. Disable this option only if you want to simulate a specific FLASH interface that requires aligned read access. |
|
Enable QSPI-NOR support on the STM32 family of processors. |
|
Enable framebuffer-based display ‘helper’ driver. |
|
Enable driver for the FXAS21002 gyroscope |
|
Selects the output data rate 0: 800 Hz 1: 400 Hz 2: 200 Hz 3: 100 Hz 4: 50 Hz 5: 25 Hz 6: 12.5 Hz 7: 12.5 Hz |
|
Say Y to route data ready interrupt to INT1 pin. Say N to route to INT2 pin. |
|
Selects the full scale range 0: +/-2000 dps (62.5 mdps/LSB) 1: +/-1000 dps (31.25 mdps/LSB) 2: +/-500 dps (15.625 mdps/LSB) 3: +/-250 dps (7.8125 mdps/LSB) |
|
Own thread priority |
|
Own thread stack size |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
The datasheet defines the value of the WHOAMI register, but some pre-production devices can have a different value. It is unlikely you should need to change this configuration option from the default. |
|
Enable driver for the FXOS8700 accelerometer/magnetometer. The driver also supports MMA8451Q, MMA8652FC and MMA8653FC accelerometers. If the driver is used with one of these accelerometers then the Accelerometer-only mode should be selected.” |
|
Say Y to route data ready interrupt to INT1 pin. Say N to route to INT2 pin. |
|
Enable magnetic vector-magnitude detection |
|
Say Y to route magnetic vector-magnitude interrupt to INT1 pin. Say N to route to INT2 pin. |
|
Accelerometer-only mode |
|
Hybrid (accel+mag) mode |
|
Magnetometer-only mode |
|
Enable motion detection |
|
Say Y to route motion interrupt to INT1 pin. Say N to route to INT2 pin. |
|
Enable pulse detection |
|
Say Y to route pulse interrupt to INT1 pin. Say N to route to INT2 pin. |
|
Enable the temperature sensor. Note that the temperature sensor is uncalibrated and its output for a given temperature may vary from one device to the next. |
|
Own thread priority |
|
Own thread stack size |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
Enable driver for GD7965 compatible controller. |
|
The ARM Generic Interrupt Controller v1 (e.g. PL390) works with the ARM Cortex-family processors. |
|
The ARM Generic Interrupt Controller v2 (e.g. GIC-400) works with the ARM Cortex-family processors. |
|
The ARM Generic Interrupt Controller v3 (e.g. GIC-500 and GIC-600) works with the ARM Cortex-family processors. |
|
Include GPIO drivers in system config |
|
Enable the TI SimpleLink CC13xx / CC26xx GPIO driver. |
|
Enable the GPIO driver on TI SimpleLink CC32xx boards |
|
Enable config options to support the ARM CMSDK GPIO controllers. Says n if not sure. |
|
Enable driver for Designware GPIO |
|
Include Designware GPIO driver |
|
Clock controller’s subsystem |
|
When interrupts fire, the driver’s ISR function is being called directly. |
|
When interrupts fire, the shared IRQ driver is notified. Then the shared IRQ driver dispatches the interrupt to other drivers. |
|
Include Designware GPIO driver |
|
Clock controller’s subsystem |
|
When interrupts fire, the driver’s ISR function is being called directly. |
|
When interrupts fire, the shared IRQ driver is notified. Then the shared IRQ driver dispatches the interrupt to other drivers. |
|
Include Designware GPIO driver |
|
Clock controller’s subsystem |
|
When interrupts fire, the driver’s ISR function is being called directly. |
|
When interrupts fire, the shared IRQ driver is notified. Then the shared IRQ driver dispatches the interrupt to other drivers. |
|
Include Designware GPIO driver |
|
Clock controller’s subsystem |
|
When interrupts fire, the driver’s ISR function is being called directly. |
|
When interrupts fire, the shared IRQ driver is notified. Then the shared IRQ driver dispatches the interrupt to other drivers. |
|
Enable clock gating |
|
Device driver initialization priority. |
|
Enable the emulated GPIO driver. Mainly used for testing, this driver allows for an arbitrary number of emulated GPIO controllers to be instantiated. Furthermore, the emulated pins can be “wired” using the regular GPIO callback API and the additional API available in drivers/gpio/gpio_emul.h . Configuration for each GPIO instance is accomplished using device tree and an example of such a configuration is in tests/drivers/gpio/gpio_basic_api/boards/native_posix_64.overlay If unsure, say N. |
|
Enables the ESP32 GPIO driver |
|
Include support for GPIO pins 0-31 on the ESP32. |
|
Include support for GPIO pins 32-39 on the ESP32. |
|
Select the IRQ line to be used for GPIO interrupts. Edge-triggered interrupts are supported on lines: 10, 22, 28, 30. Level-triggered interrupts are supported on lines: 0-5, 8, 9, 12, 13, 17-21, 23-27, 31. |
|
Enable the Gecko gpio driver. |
|
Common initialization priority |
|
Enable keyscan driver for HT16K33. The HT16K33 is a memory mapping, multifunction LED controller driver. The controller supports matrix key scan circuit of up to 13x3 keys. The keyscan functionality is exposed as up to 3 GPIO controller drivers, each supporting GPIO callbacks for keyscan event notifications. |
|
Device driver initialization priority. This driver must be initialized after the HT16K33 LED driver. |
|
Enable the IMX GPIO driver. |
|
Enable driver for Intel Apollo Lake SoC GPIO |
|
This option enables the checks to make sure the GPIO pin can be manipulated. Only if the pin is owned by the host software and its functioning as GPIO, then the driver allows manipulating the pin. Say y if unsure. |
|
Enable driver for the ite GPIO controller. |
|
Enable Litex GPIO driver. |
|
Enable GPIO driver for LMP90xxx. The LMP90xxx is a multi-channel, low power sensor analog frontend (AFE). The GPIO port of the LMP90xxx (D6 to D0) is exposed as a GPIO controller driver with read/write support. |
|
Device driver initialization priority. This driver must be initialized after the LMP90xxx ADC driver. |
|
Enable GPIO driver for LPC11U6x MCUs. |
|
Enable driver for MCP23S17 SPI-based GPIO chip. |
|
Device driver initialization priority. |
|
Enable the MCUX pinmux driver. |
|
Enable the MCUX IGPIO driver. |
|
Enable the MCUX LPC pinmux driver. |
|
Enable Port 0. |
|
Enable Port 1. |
|
This is a driver for accessing a simple, fixed purpose, 32-bit memory-mapped i/o register using the same APIs as GPIO drivers. This is useful when an SoC or board has registers that aren’t part of a GPIO IP block and these registers are used to control things that Zephyr normally expects to be specified using a GPIO pin, e.g. for driving an LED, or chip-select line for an SPI device. |
|
Enable support for NPCX GPIO driver. |
|
Enable GPIO driver for nRF line of MCUs. |
|
Initialization priority for nRF GPIO. |
|
Enable nRF GPIO port P0 config options. |
|
Enable nRF GPIO port P1 config options. |
|
Enable driver for PCA95XX I2C-based GPIO chip. |
|
Device driver initialization priority. |
|
Enable interrupt support in PCA95XX driver. Note that the PCA95XX cannot reliably detect short-pulse interrupts due to its design. |
|
Enable support for the Cypress PSoC-6 GPIO controllers. |
|
Enable the RV32M1 GPIO driver. |
|
Enable support for the Atmel SAM ‘PORT’ GPIO controllers. |
|
Enable support for the Atmel SAM0 ‘PORT’ GPIO controllers. |
|
Enable support for the Atmel SAM4L ‘PORT’ GPIO controllers. |
|
Enable GPIO Shell for testing. |
|
Enable driver for the SiFive Freedom GPIO controller. Says n if not sure. |
|
Enable support for the Stellaris GPIO controllers. |
|
Enable GPIO driver for STM32 line of MCUs |
|
JTAG-DP Disabled and SW-DP Disabled |
|
Full SWJ (JTAG-DP + SW-DP): Reset State |
|
JTAG-DP Disabled and SW-DP Enabled |
|
Full SWJ (JTAG-DP + SW-DP) but without NJTRST |
|
Enable driver for SX1509B I2C GPIO chip. |
|
Debounce time interval when debounce enabled. A value V produces a multiplier of 0.5 ms * 2^V, which is then scaled by 2 MHz / fOSC. See the datasheet for details. |
|
Device driver initialization priority. |
|
Enable support for interrupts on GPIO pins. |
|
Enable the Microchip XEC gpio driver. |
|
Enable Xilinx AXI GPIO v2 driver. |
|
Setting this value will enable driver support for the Groove-LCD RGB Backlight. |
|
Specify the device name of the I2C master device to which the Grove LCD is connected. |
|
Setting this value will enable driver support for the Grove Light Sensor. |
|
Setting this value will enable driver support for the Grove Temperature Sensor. |
|
Enable GSM 07.10 muxing protocol defined in https://www.etsi.org/deliver/etsi_ts/101300_101399/101369/07.01.00_60/ts_101369v070100p.pdf The muxing protocol allows GSM modem to share the same UART for both the PPP data and AT commands. |
|
Channel number for the AT commands to the modem. |
|
For our purposes we will manage with 3 DLCI (control, ppp, and AT commands) so making it the default value. If GSM modem also provides GNSS (location) services and you want to create a DLCI for it, then you need to increase this to 4. |
|
Channel number for the PPP connection to the modem. SIMCOM modem has 16kb buffer for DLCI 1 so the manual recommends it for PPP traffic. For other DLCIs in that modem, the buffer size is only 1kb. |
|
Default value when deciding whether we are the initiator of the connection attempt. Normally this should be enabled. |
|
Usually we only need one GSM mux instance. You need to increase this if you have more than one GSM modems. |
|
Default MRU (Maximum Receive Unit) data size. The default value for Basic mode is 31 bytes. The 1509 limit comes from ublox-sara modem and it means we can transfer full Ethernet sized frame and muxing headers. |
|
Max MRU (Maximum Receive Unit) data size. The default max value for Basic mode is 128 bytes. |
|
How many pending GSM mux commands can exists. |
|
T1 timeout is initial command timeout when establishing the connection. The value is in milliseconds. Zero value means that default (100 ms) specified in the code is used. |
|
As there might be lot of debug output printed, only enable this if really needed. |
|
Indicates that the platform supports SEGGER J-Link RTT. |
|
Signifies whether DesignWare SPI compatible HW is available |
|
Enable driver for HMC5883L I2C-based magnetometer. |
|
Magnetometer full-scale range. An X value for the config represents a range of +/- X gauss. Valid values are 0.88, 1.3, 1.9, 2.5, 4, 4.7, 5.6 and 8.1. |
|
Magnetometer output data rate expressed in samples per second. Data rates supported by the chip are 0.75, 1.5, 3, 7.5, 15, 30 and 75. |
|
Priority of thread used by the driver to handle interrupts. |
|
Stack size of thread used by the driver to handle interrupts. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
Enable HopeRF HP206C barometer and altimeter support. |
|
Value, in cm, that will be used to compensate altitude calculation. For more info on how to choose this value, consult section 6.1.1 in the datasheet. |
|
Altitude offset set at runtime |
|
Allowed values: 4096, 2048, 1024, 512, 256, 128 |
|
Oversampling rate set at runtime |
|
This option selects High Precision Event Timer (HPET) as a system timer. |
|
Enable LED driver for HT16K33. The HT16K33 is a memory mapping, multifunction LED controller driver. The controller supports up to 128 LEDs (up to 16 rows and 8 commons). |
|
Enable keyscan child device support in the HT16K33 LED driver. The keyscan functionality itself is handled by the HT16K33 GPIO driver. |
|
Keyscan debounce interval in milliseconds. |
|
Priority level for internal thread for keyscan interrupt processing. |
|
Size of the stack used for internal thread for keyscan interrupt processing. |
|
Keyscan poll interval in milliseconds. Polling is only used if no interrupt line is present. |
|
Enable driver for HTS221 I2C-based temperature and humidity sensor. |
|
Sensor output data rate expressed in samples per second. Data rates supported by the chip are 1, 7 and 12.5. |
|
Priority of thread used by the driver to handle interrupts. |
|
Stack size of thread used by the driver to handle interrupts. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
Enable hwinfo driver. |
|
Enable ESP32 hwinfo driver. |
|
Enable NXP i.mx RT hwinfo driver. |
|
Enable LiteX hwinfo driver |
|
Enable NXP kinetis mcux hwinfo driver. |
|
Enable Nordic NRF hwinfo driver. |
|
Enable Cypress PSoC-6 hwinfo driver. |
|
Enable Atmel SAM hwinfo driver. |
|
Enable Atmel SAM0 hwinfo driver. |
|
Enable Atmel SAM4L hwinfo driver. |
|
Enable hwinfo Shell for testing. |
|
Enable STM32 hwinfo driver. |
|
Enable I2C Driver Configuration |
|
Enable I2C Port 0 |
|
IRQ priority. |
|
Enable nRF TWI Master without EasyDMA on port 0. |
|
Enable nRF TWI Master with EasyDMA on port 0. This peripheral accepts transfers from RAM only, if provided buffer is placed in flash, transfer will fail. |
|
Enable I2C Port 1 |
|
Enable nRF TWI Master without EasyDMA on port 1. |
|
Enable nRF TWI Master with EasyDMA on port 1. This peripheral accepts transfers from RAM only, if provided buffer is placed in flash, transfer will fail. |
|
Enable nRF TWI Master with EasyDMA on port 2. This peripheral accepts transfers from RAM only, if provided buffer is placed in flash, transfer will fail. |
|
Enable nRF TWI Master with EasyDMA on port 3. This peripheral accepts transfers from RAM only, if provided buffer is placed in flash, transfer will fail. |
|
Enable library used for software driven (bit banging) I2C support |
|
Enable support for I2C on the TI SimpleLink CC13xx / CC26xx series. |
|
Enable the CC32XX I2C driver. |
|
Enable the Design Ware I2C driver |
|
Set the clock speed for I2C |
|
The maximum number of supported driver instances in device tree. |
|
Enable virtual I2C Slave EEPROM driver |
|
Enable the I2C emulator driver. This is a fake driver in that it does not talk to real hardware. Instead it talks to emulation drivers that pretend to be devices on the emulated I2C bus. It is used for testing drivers for I2C devices. |
|
Enables the ESP32 I2C driver |
|
Port 0 IRQ line |
|
Port 0 Receive LSB first |
|
Port 0 Transmit LSB first |
|
Port 1 IRQ line |
|
Port 1 Receive LSB first |
|
Port 1 Transmit LSB first |
|
I2C timeout to receive a data bit in APB clock cycles |
|
Enable the SiLabs Gecko I2C bus driver. |
|
Enable software driven (bit banging) I2C support using GPIO pins |
|
Enable the i.MX I2C driver. |
|
I2C device driver initialization priority. |
|
Enable I2C support on it8xxx2_evb. Supported Speeds: 100kHz, 400kHz and 1MHz. This driver supports repeated start. |
|
Enable support for Litex I2C driver |
|
Enable I2C support on the LPC11U6X SoCs |
|
Enable the mcux I2C driver. |
|
Enable the mcux flexcomm i2c driver. |
|
Enable the mcux LPI2C driver. |
|
Enable the Nios-II I2C driver. |
|
Enable support for NPCX I2C driver. The NPCX SMB/I2C modules provides full support for a two-wire SMBus/I2C synchronous serial interface. Each interface is a two-wire serial interface that is compatible with both Intel SMBus and Philips I2C physical layer. There are 8 SMBus modules and 10 buses in NPCX7 series. |
|
Enable support for nrfx TWI drivers for nRF MCU series. |
|
Enable the RV32M1 LPI2C driver. |
|
Enable the SAM0 series SERCOM I2C driver. |
|
This enables DMA driven transactions for the I2C peripheral. DMA driven mode requires fewer interrupts to handle the transaction and ensures that high speed modes are not delayed by data reloading. |
|
Enable Atmel SAM MCU Family (TWI) I2C bus driver. |
|
Enable Atmel SAM MCU Family (TWIHS) I2C bus driver. |
|
Enable Atmel SAM MCU Family (TWIM) I2C bus driver. |
|
I2C driver for ARM’s SBCon two-wire serial bus interface |
|
Enable I2C Shell. The I2C shell currently support scanning and bus recovery. |
|
Enable I2C support on SiFive Freedom |
|
Enable I2C Slave Driver Configuration |
|
I2C Slave device driver initialization priority. |
|
Enable I2C support on the STM32 SoCs |
|
Enable Interrupt support for the I2C Driver |
|
Enable I2C support on the STM32 F1 and F4X family of processors. This driver also supports the F2 and L1 series. |
|
Enable I2C support on the STM32 F0, F3, F7, L4, WBX, MP1, G0, G4 and H7 family of processors. This driver also supports the L0 series. If I2C_SLAVE is enabled it selects I2C_STM32_INTERRUPT, since slave mode is only supported by this driver with interrupts enabled. |
|
Enable the Microchip XEC I2C driver. |
|
Enable support for the I2S (Inter-IC Sound) hardware bus. |
|
Enable Inter Sound (I2S) bus driver for Intel_S1000 based on Synchronous Serial Port (SSP) module. |
|
Device driver initialization priority. |
|
Enable Litex Inter Sound (I2S) bus driver. |
|
Channels placed without padding in fifo |
|
Received data will be stored as big endian |
|
RX queue length |
|
TX queue length |
|
Enable Inter Sound (I2S) bus driver for Atmel SAM MCU family based on Synchronous Serial Controller (SSC) module. |
|
If enabled RF signal is connected to RF pin. It will be configured as an output or an input depending on whether the receiver is working in master or slave mode. If disabled RF signal is disconnected from RF pin and connected internally to TF (Transmitter Frame Synchro signal). |
|
If enabled RK signal is connected to RK pin. It will be configured as an output or an input depending on whether the receiver is working in master or slave mode. If disabled RK signal is disconnected from RK pin and connected internally to TK (Transmitter Clock signal). |
|
RX queue length |
|
TX queue length |
|
Enable I2S support on the STM32 family of processors. (Tested on the STM32F4 series) |
|
Division factor for the audio PLL (PLLI2S) VCO input clock. PLLM factor should be selected to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit PLL jitter. Allowed values: 2-63 |
|
Multiply factor for the audio PLL (PLLI2S) VCO output clock. PLLN factor should be selected to ensure that the VCO output frequency ranges from 100 to 432 MHz. Allowed values: 50-432 |
|
Division factor for the I2S clock. PLLR factor should be selected to ensure that the I2S clock frequency is less than or equal to 192MHz. Allowed values: 2-7 |
|
RX queue length |
|
TX queue length |
|
Enable it if I2S clock should be provided by the PLLI2S. If not enabled the clock will be provided by HSI/HSE. |
|
Number of retries when reading failed or device not ready. |
|
Enable driver for ICM42605 SPI-based six-axis motion tracking device. |
|
Priority of thread used by the driver to handle interrupts. |
|
Stack size of thread used by the driver to handle interrupts. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
IEEE 802.15.4 drivers options |
|
TI CC1200 Driver support |
|
Set the CCA threshold. See datasheet’s AGC_CS_THR register for more information. Do not touch this unless you know what you are doing. |
|
This option sets the driver name |
|
Set the initialization priority number. Do not mess with it unless you know what you are doing. Beware cc1200 requires gpio and spi to be ready first (and sometime gpio should be the very first as spi might need it too). And of course it has to start before the net stack. |
|
This is the byte 4 of the MAC address. |
|
This is the byte 5 of the MAC address. |
|
This is the byte 6 of the MAC address. |
|
This is the byte 7 of the MAC address. |
|
Generate a random MAC address dynamically. |
|
Use TI CC1200 RF pre-sets |
|
868MHz - 50Kbps - 2-GFSK - IEEE 802.15.4g compliant - ETSI |
|
920MHz - 50Kbps - 2-GFSK - IEEE 802.15.4g compliant - ARIB |
|
434MHz - 50Kbps - 2-GFSK - IEEE 802.15.4g compliant - ETSI |
|
Set the gain adjustment. See datasheet’s AGC_GAIN_ADJUST register for more information. Do not touch this unless you know what you are doing. |
|
This option sets the driver’s stack size for its internal RX thread. The default value should be sufficient, but in case it proves to be a too little one, this option makes it easy to play with the size. |
|
This sets the XOSC value, it must be between 38400 and 40000. This value should follow what has been set in the RF settings via SmartRF tool. Do not touch this unless you know what you are doing. |
|
TI CC13xx / CC26xx IEEE 802.15.4 driver support |
|
This option sets the driver name. |
|
Set the initialization priority number. |
|
The maximum value of the backoff exponent (BE) in the CSMA-CA algorithm. |
|
The maximum number of backoffs the CSMA-CA algorithm will attempt before declaring a channel access failure. |
|
The minimum value of the backoff exponent (BE) in the CSMA-CA algorithm. |
|
Number of transmission attempts radio driver should do, before replying it could not send the packet. |
|
TI CC13xx / CC26xx IEEE 802.15.4g driver support |
|
This option sets RSSI threshold for carrier sense in the CSMA/CA algorithm. |
|
This option sets the driver name. |
|
Set the initialization priority number. |
|
This option allows the user to configure the number of receive buffers. |
|
Number of transmission attempts radio driver should do, before replying it could not send the packet. |
|
TI CC2520 Driver support |
|
This option will expose the hardware AES encryption from CC2520. Such feature should not be used for anything but 802.15.4 security. The crypto device exposed will only support synchronous CCM operation. |
|
This option sets the driver name for the crypto part found on CC2520. |
|
Set the initialization priority number. Do not mess with it unless you know what you are doing. It should be initialized after CC2520 as it shares the same runtime context. |
|
This option sets the driver name |
|
Set the initialization priority number. Do not mess with it unless you know what you are doing. Beware cc2520 requires gpio and spi to be ready first (and sometime gpio should be the very first as spi might need it too). And of course it has to start before the net stack. |
|
This is the byte 4 of the MAC address. |
|
This is the byte 5 of the MAC address. |
|
This is the byte 6 of the MAC address. |
|
This is the byte 7 of the MAC address. |
|
Generate a random MAC address dynamically. |
|
This option sets the driver’s stack size for its internal RX thread. The default value should be sufficient, but in case it proves to be a too little one, this option makes it easy to play with the size. |
|
Decawave DW1000 Driver support |
|
Set the initialization priority number. Do not mess with it unless you know what you are doing. Beware DW1000 requires gpio and spi to be ready first (and sometime gpio should be the very first as spi might need it too). And of course it has to start before the net stack. |
|
SNIFF off time in unit of approximate 1 microsecond. |
|
SNIFF on time in unit of PAC. The minimum on time is the duration of two PACs. The SNIFF counter always adds 1 PAC unit to the on-time count. The SNIFF_ONT value should be in range of 1-15. Zero value disables SNIFF mode. |
|
NXP KW41Z Driver support |
|
This option sets the driver name. Do not change it unless you know what you are doing. |
|
Set the initialization priority number. Do not change it unless you know what you are doing. It has to start before the net stack. |
|
NXP MCR20A Driver support |
|
This option sets the driver name |
|
Set the initialization priority number. Do not mess with it unless you know what you are doing. Beware mcr20a requires gpio and spi to be ready first (and sometime gpio should be the very first as spi might need it too). And of course it has to start before the net stack. |
|
This option sets the driver’s stack size for its internal RX thread. The default value should be sufficient, but in case it proves to be a too little one, this option makes it easy to play with the size. |
|
This option allows user to set any configuration and/or filter before the radio becomes operational. For instance, the EUI-64 value can be configured using net_if_set_link_addr(iface, mac, 8, NET_LINK_IEEE802154). When all configurations are done net_if_up() has to be invoked to bring the interface up. This option can be useful when using OpenThread or Zigbee. If you have any doubt about this option leave it as default value. |
|
nRF52 series IEEE 802.15.4 Driver |
|
This option sets the driver name |
|
The driver may manage radio IRQs by itself, or use an external radio IRQ provider. When radio IRQs are managed by an external provider, the driver shall not configure radio IRQs. Enable this option when external radio IRQ provider is enabled in the system. One example of external radio IRQ provider could be a radio arbiter used in dynamic multiprotocol applications. |
|
Set the initialization priority number. Do not mess with it unless you know what you are doing. |
|
Enable TX time support. This is needed when upper layers want to set the exact time when the packet should be sent. |
|
This option sets the driver’s stack size for its internal RX thread. The default value should be sufficient, but in case it proves to be a too little one, this option makes it easy to play with the size. |
|
This option enables using the drivers in a so-called “raw” mode, i.e. without a MAC stack (the net L2 layer for 802.15.4 will not be built). Used only for very specific cases, such as wpan_serial and wpanusb samples. |
|
PHY is a ranging-capable device (RDEV) |
|
ATMEL RF2XX Driver support |
|
This option sets the driver name |
|
Set the initialization priority number. Do not mess with it unless you know what you are doing. Beware rf2xx requires gpio and spi to be ready first (and sometime gpio should be the very first as spi might need it too). And of course it has to start before the net stack. |
|
This option sets the driver’s stack size for its internal RX thread. The default value should be sufficient, but in case it proves to be a too little one, this option makes it easy to play with the size. |
|
UART PIPE fake radio driver support for QEMU |
|
UART PIPE Driver name |
|
This option assure the driver will process just frames addressed to him. |
|
This is the byte 4 of the MAC address. |
|
This is the byte 5 of the MAC address. |
|
This is the byte 6 of the MAC address. |
|
This is the byte 7 of the MAC address. |
|
Generate a random MAC address dynamically. |
|
Custom vendor OUI, which makes 24 most-significant bits of MAC address |
|
This option enables setting custom vendor OUI using IEEE802154_VENDOR_OUI. After enabling, user is obliged to set IEEE802154_VENDOR_OUI value, as this option has no default value. |
|
Enable driver for IIS2DH accelerometer sensor driver |
|
Specify the default accelerometer output data rate expressed in samples per second (Hz). 0: ODR selected at runtime 1: 1 Hz 2: 10 Hz 3: 25 Hz 4: 50 Hz 5: 100 Hz 6: 200 Hz 7: 400 Hz 8: 1620 Hz (only LP) 9: Depends by mode. LP: 5376 Hz - NORM or HR: 1344 Hz |
|
Specify the sensor power mode 0: High Resolution mode 1: Normal mode 2: Low Power mode |
|
Specify the default accelerometer full-scale range. Valid values are: 0: Full Scale selected at runtime 2: +/- 2g 4: +/- 4g 8: +/- 8g 16: +/- 16g |
|
Priority of thread used by the driver to handle interrupts. |
|
Stack size of thread used by the driver to handle interrupts. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
Enable driver for IIS2DLPC accelerometer sensor driver |
|
Enable tap (single/double) detection |
|
Priority of thread used by the driver to handle interrupts. |
|
Stack size of thread used by the driver to handle interrupts. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
Enable driver for IIS2ICLX accelerometer sensor. |
|
Specify the default accelerometer full-scale range. An X value for the config represents a range of +/- X G. Valid values are: 0: Full Scale selected at runtime 500: +/- 500mg 1000: +/- 1g 2000: +/- 2g 3000: +/- 3g |
|
Specify the default accelerometer output data rate expressed in samples per second (Hz). 0: ODR selected at runtime 1: 12.5Hz 2: 26Hz 3: 52Hz 4: 104Hz 5: 208Hz 6: 416Hz 7: 833Hz 8: 1660Hz 9: 3330Hz 10: 6660Hz |
|
Enable/disable temperature |
|
Enable HTS221 as external sensor |
|
Enable IIS2MDC as external sensor |
|
Enable LIS2MDL as external sensor |
|
Enable LPS22HB as external sensor |
|
Enable LPS22HH as external sensor |
|
Enable/disable internal sensorhub. You can enable a maximum of two external sensors (if more than two are enabled the system would enumerate only the first two found) |
|
Priority of thread used by the driver to handle interrupts. |
|
Stack size of thread used by the driver to handle interrupts. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
Enable driver for IIS2MDC I2C-based magnetometer sensor. |
|
Set magnetometer sampling frequency (ODR) at runtime (default: 10 Hz) |
|
Enable SPI 4wire mode (separated MISO and MOSI lines) |
|
Priority of thread used by the driver to handle interrupts. |
|
Stack size of thread used by the driver to handle interrupts. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
Enable driver for IIS3DHHC SPI-based accelerometer sensor. |
|
Say Y to route data ready interrupt to INT1 pin. Say N to route to INT2 pin. |
|
Enable Sensor at 1KHz |
|
Priority of thread used by the driver to handle interrupts. |
|
Stack size of thread used by the driver to handle interrupts. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
Enable driver for ILI9340 display driver. |
|
Enable driver for ILI9488 display driver. |
|
Hidden configuration entry for all ILI9XXX drivers. |
|
Enable support for Intel’s GMM and Neural Network Accelerator |
|
Device driver initialization priority. |
|
Max. number of unique neural network models required in the system |
|
Maximum number of pending inference requests in the driver |
|
Sets GNA operation mode for power saving Levels are: 0 ALWAYS_ON, GNA is always on with very minimal power save 1 CLOCK_GATED, GNA clock is gated when not active 2 POWER_GATED, GNA clock and power are gated when not active 3 ALWAYS_OFF, GNA is tuned off and never used in the system |
|
Such interrupt remapping hardware is provided through Intel VT-D technology. It’s being used, currently, only for MSI/MSI-X multi-vector support. If you have such PCIe device requiring multi-vector support, you will need to enable this. |
|
This device should be initialized as soon as possible, before any other device that would require it for MSI/MSI-X multi-vector support. |
|
This option signifies that the target has an IO-APIC device. This capability allows IO-APIC-dependent code to be included. |
|
At boot, mask all IOAPIC RTEs if they may be in an undefined state. You don’t need this if the RTEs are either all guaranteed to be masked when the OS starts up, or a previous boot stage has done some IOAPIC configuration that needs to be preserved. |
|
This option indicates the maximum number of Redirection Table Entries (RTEs) (one per IRQ available to the IO-APIC) made available to the kernel, regardless of the number provided by the hardware itself. For most efficient usage of memory, it should match the number of IRQ lines needed by devices connected to the IO-APIC. |
|
Include interrupt-based inter-processor mailboxes drivers in system configuration |
|
Driver for the Intra-DSP Communication (IDC) channel for cross SoC communications. |
|
Enable console over Inter-processor Mailbox. |
|
IPM console line buffer length specify amount of the buffer where characters are stored before sending the whole line. |
|
IPM device name used by IPM console driver. |
|
Enable the receiving side of IPM console |
|
Enable the sending side of IPM console |
|
Each instance of the IPM console receiver driver creates a worker thread to print out incoming messages from the remote CPU. Specify the stack size for these threads here. |
|
Driver for NXP i.MX messaging unit |
|
There will be a single message type with id 0 and a maximum size of 16 bytes. |
|
There will be four message types with ids 0, 1, 2 or 3 and a maximum size of 4 bytes each. |
|
There will be two message types with ids 0 or 1 and a maximum size of 8 bytes each. |
|
Driver for the Host-DSP Mailbox Communication channel. |
|
Driver for MCUX mailbox |
|
Driver for SSE 200 MHU (Message Handling Unit) |
|
Enable IPM Message Channel 0 |
|
IPM Message RX Channel |
|
IPM Message TX Channel |
|
Enable IPM Message Channel 10 |
|
IPM Message RX Channel |
|
IPM Message TX Channel |
|
Enable IPM Message Channel 11 |
|
IPM Message RX Channel |
|
IPM Message TX Channel |
|
Enable IPM Message Channel 12 |
|
IPM Message RX Channel |
|
IPM Message TX Channel |
|
Enable IPM Message Channel 13 |
|
IPM Message RX Channel |
|
IPM Message TX Channel |
|
Enable IPM Message Channel 14 |
|
IPM Message RX Channel |
|
IPM Message TX Channel |
|
Enable IPM Message Channel 15 |
|
IPM Message RX Channel |
|
IPM Message TX Channel |
|
Enable IPM Message Channel 1 |
|
IPM Message RX Channel |
|
IPM Message TX Channel |
|
Enable IPM Message Channel 2 |
|
IPM Message RX Channel |
|
IPM Message TX Channel |
|
Enable IPM Message Channel 3 |
|
IPM Message RX Channel |
|
IPM Message TX Channel |
|
Enable IPM Message Channel 4 |
|
IPM Message RX Channel |
|
IPM Message TX Channel |
|
Enable IPM Message Channel 5 |
|
IPM Message RX Channel |
|
IPM Message TX Channel |
|
Enable IPM Message Channel 6 |
|
IPM Message RX Channel |
|
IPM Message TX Channel |
|
Enable IPM Message Channel 7 |
|
IPM Message RX Channel |
|
IPM Message TX Channel |
|
Enable IPM Message Channel 8 |
|
IPM Message RX Channel |
|
IPM Message TX Channel |
|
Enable IPM Message Channel 9 |
|
IPM Message RX Channel |
|
IPM Message TX Channel |
|
Driver for Nordic nRF messaging unit, based on nRF IPC peripheral HW. |
|
Enable this option if the IPM device should have a single instance, instead of one per IPC message channel. |
|
Driver for stm32 IPCC mailboxes |
|
use to define the Processor ID for IPCC access |
|
Enable driver for the ISL29035 light sensor. |
|
105 ms |
|
0.0256 ms |
|
0.41 ms |
|
6.5 ms |
|
1 |
|
16 |
|
4 |
|
8 |
|
16000 |
|
1000 |
|
4000 |
|
64000 |
|
Sensing mode for ambient light spectrum. |
|
Sensing mode for infrared spectrum. |
|
Priority of thread used to handle the timer and threshold triggers. |
|
Stack size of thread used by the driver to handle interrupts. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
Enable driver for ISM330DHCX accelerometer and gyroscope sensor. |
|
Specify the default accelerometer full-scale range. An X value for the config represents a range of +/- X G. Valid values are: 0: Full Scale selected at runtime 2: +/- 2g 4: +/- 4g 8: +/- 8g 16: +/- 16g |
|
Specify the default accelerometer output data rate expressed in samples per second (Hz). 0: ODR selected at runtime 1: 12.5Hz 2: 26Hz 3: 52Hz 4: 104Hz 5: 208Hz 6: 416Hz 7: 833Hz 8: 1660Hz 9: 3330Hz 10: 6660Hz |
|
Enable/disable temperature |
|
Enable HTS221 as external sensor |
|
Enable IIS2MDC as external sensor |
|
Enable LIS2MDL as external sensor |
|
Enable LPS22HB as external sensor |
|
Enable LPS22HH as external sensor |
|
Specify the default gyroscope full-scale range. An X value for the config represents a range of +/- X degree per second. Valid values are: 0: Full Scale selected at runtime 125: +/- 125dps 250: +/- 250dps 500: +/- 500dps 1000: +/- 1000dps 2000: +/- 2000dps |
|
Specify the default accelerometer output data rate expressed in samples per second (Hz). 0: ODR selected at runtime 1: 12.5Hz 2: 26Hz 3: 52Hz 4: 104Hz 5: 208Hz 6: 416Hz 7: 833Hz 8: 1660Hz 9: 3330Hz 10: 6660Hz |
|
int1 |
|
int2 |
|
Enable/disable internal sensorhub. You can enable a maximum of two external sensors (if more than two are enabled the system would enumerate only the first two found) |
|
Priority of thread used by the driver to handle interrupts. |
|
Stack size of thread used by the driver to handle interrupts. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
Enable Wurth Elektronik WSEN-ITDS 3-axis acceleration sensor provides acceleration and die temperature measurement. |
|
Set to enable trigger mode using gpio interrupt, interrupts are configured to line INT0. |
|
Configures the maximum number of clients allowed per shared instance of the shared interrupt driver. To conserve RAM set this value to the lowest practical value. this software interrupt default set on by device tree. |
|
This module implements a kernel device driver for the ITE it8xxx2 HW timer model |
|
This will enable support of qemu’s ivshmem device, which is also present in ACRN hypervizor, and lets VM sharing memory with each other. |
|
This will enable support of ivshmem-doorbell, i.e. the interrupt based ivshmem. |
|
Interrupt priority used for the MSI-X generated interrupts. |
|
MSI-X vector holders must be pre-allocated. One can pre-allocate more or less than necessary. Depends on how many VMs will connect with each other. These are know to be the notification vectors in ivshmem. |
|
This is mostly a module to help getting info the ivshmem and/or quickly testing your ivshmem client application (from another VM). |
|
Enable IWDG driver for STM32 line of MCUs |
|
Set initial timeout value for IWDG in ms if enabled at boot. The min timeout supported is 1 ms. The max timeout depends on the MCU’s LSI clock frequency and can be calculated with:
Limiting maximum timeout to a safe value of 26214 ms here, which was calculated for highest LSI frequency among STM32 MCUs of 40 kHz. |
|
Include Keyboard scan drivers in system config. |
|
Enable driver for multiple Focaltech capacitive touch panel controllers. This driver should support FT5x06, FT5606, FT5x16, FT6x06, Ft6x36, FT5x06i, FT5336, FT3316, FT5436i, FT5336i and FT5x46. |
|
Enable interrupt support (requires GPIO). |
|
Sample period in milliseconds when in polling mode. |
|
Keyboard scan device driver initialization priority. |
|
Enable driver for the SDL mouse event filter. |
|
Enable the Microchip XEC Kscan IO driver. |
|
Adjust the value to your keyboard columns. The maximum column size for the Microchip XEC family is 18 (from 0 to 17). |
|
Determines the time in msecs for debouncing a key press. |
|
Determines the time in msecs for debouncing a key release. |
|
Defines the poll period in msecs between between matrix scans. |
|
Adjust the value to your keyboard rows. The maximum column size for the Microchip XEC family is 8 (from 0 to 7). |
|
The value depends on your debugging needs. This generates an encoded trace of events without going to debug logging to avoid timing impact on running code. The buffer is post analyzed via the debugger. |
|
Include LED drivers in the system configuration. |
|
System initialization priority for LED drivers. |
|
Enable driver for PWM LEDs. |
|
Enable LED shell for testing. |
|
Include LED strip drivers in the system configuration. |
|
System initialization priority for LED strip drivers. |
|
This module implements a kernel device driver for the GRLIB GPTIMER which is common in LEON systems. |
|
GRLIB IRQMP and IRQAMP |
|
Enable the Gecko leuart driver. |
|
Enable SPI/I2C-based driver for LIS2DH, LIS3DH, LSM303DLHC, LIS2DH12, LSM303AGR triaxial accelerometer sensors. |
|
+/-16g |
|
+/-2g |
|
+/-4g |
|
+/-8g |
|
Set at runtime |
|
1Hz |
|
10Hz |
|
25Hz |
|
50Hz |
|
100Hz |
|
200Hz |
|
400Hz |
|
1.6KHz |
|
5KHz |
|
1.25KHz |
|
Set at runtime |
|
high resolution (12 bit) |
|
low power (8 bit) |
|
normal (10 bit) |
|
Priority of thread used by the driver to handle interrupts. |
|
Stack size of thread used by the driver to handle interrupts. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
Enable driver for LIS2DS12 accelerometer sensor driver |
|
Enable/disable temperature |
|
Specify the default accelerometer full-scale range. An X value for the config represents a range of +/- X G. Valid values are: 0: Full Scale selected at runtime 2: +/- 2g 4: +/- 4g 8: +/- 8g 16: +/- 16g |
|
Specify the default accelerometer output data rate expressed in samples per second (Hz). 0: ODR selected at runtime 1: 12.5Hz 2: 25Hz 3: 50Hz 4: 100Hz 5: 200Hz 6: 400Hz 7: 800Hz |
|
Priority of thread used by the driver to handle interrupts. |
|
Stack size of thread used by the driver to handle interrupts. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
Enable driver for LIS2DW12 accelerometer sensor driver |
|
16G |
|
2G |
|
4G |
|
8G |
|
Set at runtime (Default 2G) |
|
int1 |
|
int2 |
|
100 Hz |
|
12.5 Hz |
|
1600 Hz |
|
1.6 Hz |
|
200 Hz |
|
25 Hz |
|
400 Hz |
|
50 Hz |
|
800 Hz |
|
Set at runtime (Default 100 Hz) |
|
single |
|
Specify the sensor power mode 0: Low Power M1 1: Low Power M2 2: Low Power M3 3: Low Power M4 4: High Performance |
|
Enable pulse (single/double tap) detection |
|
When double-tap recognition is enabled, this register expresses the maximum time between two successive detected taps to determine a double-tap event. Where 0 equals 16*1/ODR and 1LSB = 32*1/ODR. |
|
Expected quiet time after a tap detection: this register represents the time after the first detected tap in which there must not be any overthreshold event. Where 0 equals 2*1/ODR and 1LSB = 4*1/ODR. |
|
Maximum duration of over-threshold event: this register represents the maximum time of an over-threshold signal detection to be recognized as a tap event. Where 0 equals 4*1/ODR and 1LSB = 8*1/ODR. |
|
Threshold to start the pulse-event detection procedure on the X-axis. Threshold values for each axis are unsigned 5-bit corresponding to an 2g acceleration full-scale range. |
|
Threshold to start the pulse-event detection procedure on the Y-axis. Threshold values for each axis are unsigned 5-bit corresponding to an 2g acceleration full-scale range. |
|
Threshold to start the pulse-event detection procedure on the Z-axis. Threshold values for each axis are unsigned 5-bit corresponding to an 2g acceleration full-scale range. |
|
Enable X axis for pulse |
|
Enable Y axis for pulse |
|
Enable Z axis for pulse |
|
single/double |
|
Priority of thread used by the driver to handle interrupts. |
|
Stack size of thread used by the driver to handle interrupts. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
Enable driver for LIS2MDL I2C-based magnetometer sensor. |
|
Set magnetometer sampling frequency (ODR) at runtime (default: 10 Hz) |
|
Enable SPI 4wire mode (separated MISO and MOSI lines) |
|
Priority of thread used by the driver to handle interrupts. |
|
Stack size of thread used by the driver to handle interrupts. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
Enable driver for LIS3MDL I2C-based magnetometer. |
|
Magnetometer full-scale range. An X value for the config represents a range of +/- X gauss. Valid values are 4, 8, 12 and 16. |
|
Magnetometer output data rate expressed in samples per second. Data rates supported by the chip are 0.625, 1.25, 2.5, 5, 10, 20, 40, 80, 155, 300, 560 and 1000. |
|
Priority of thread used by the driver to handle interrupts. |
|
Stack size of thread used by the driver to handle interrupts. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
This module implements a kernel device driver for LiteX Timer. |
|
This option selects local APIC as the interrupt controller. |
|
This option specifies the base address of the Local APIC device. |
|
A special situation may occur when a processor raises its task priority to be greater than or equal to the level of the interrupt for which the processor INTR signal is currently being asserted. If at the time the INTA cycle is issued, the interrupt that was to be dispensed has become masked (programmed by software), the local APIC will deliver a spurious-interrupt vector. Dispensing the spurious-interrupt vector does not affect the ISR, so the handler for this vector should return without an EOI. From x86 manual Volume 3 Section 10.9. |
|
IDT vector to use for spurious LOAPIC interrupts. Note that some arches (P6, Pentium) ignore the low 4 bits and fix them at 0xF. If this value is left at -1 the last entry in the IDT will be used. |
|
Include LoRa drivers in the system configuration. |
|
System initialization priority for LoRa drivers. |
|
Enable LoRa Shell for testing. |
|
Enable LoRa driver for Semtech SX1261 and SX1262. |
|
Enable LoRa driver for Semtech SX1276. |
|
Enable LoRa driver for Semtech SX12xx. |
|
Enable LED driver for LP3943. LP3943 LED driver has 16 channels each with multi-programmable states at a specified rate. Each channel can drive up to 25 mA per LED. |
|
Enable driver for the Texas Instruments LP5030 and LP5036 I2C LED controllers. They are respectively supporting up to 10 and 12 LEDs. |
|
Enable LED driver for LP5562. LP5562 LED driver has 4 channels (RGBW). Each channel can drive up to 25.5 mA per LED. |
|
Do offset calibration |
|
Enable LED strip driver for daisy chains of LPD880x (LPD8803, LPD8806, or compatible) devices. Each LPD880x LED driver chip has some output channels (3 channels for LPD8803, 6 for LPD8806), whose PWM duty cycle can be set at 7 bit resolution via a reduced SPI interface (MOSI and CLK lines only). Each chip also includes data and clock out pins for daisy chaining LED strips. |
|
Enable driver for LPS22HB I2C-based pressure and temperature sensor. |
|
Sensor output data rate expressed in samples per second. Data rates supported by the chip are 1, 10, 25, 50, 75. |
|
Enable driver for LPS22HH I2C-based pressure and temperature sensor. |
|
Sensor output data rate expressed in samples per second. Data rates supported by the chip are: 0: ODR selected at runtime 1: 1Hz 2: 10Hz 3: 25Hz 4: 50Hz 5: 75Hz 6: 100Hz 7: 200Hz |
|
Priority of thread used by the driver to handle interrupts. |
|
Stack size of thread used by the driver to handle interrupts. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
Enable driver for LPS25HB I2C-based pressure and temperature sensor. |
|
Sensor output data rate expressed in samples per second. Data rates supported by the chip are 1, 7, 13, 25. |
|
Enable driver for sharp memory display series LS0XXX7DXXX |
|
Enable driver for LSM303DLHC I2C-based triaxial magnetometer sensor. |
|
0: 0.75Hz 1: 1.5 Hz 2: 3Hz 3: 7.5Hz 4: 15Hz 5: 30Hz 6: 75Hz 7: 220Hz |
|
1: +/-1.3 gauss 2: +/-1.9 gauss 3: +/-2.5 gauss 4: +/-4 gauss 5: +/-4.7 gauss 6: +/-5.6 gauss 7: +/-8.1 gauss |
|
Enable driver for LSM6DS0 I2C-based accelerometer and gyroscope sensor. |
|
Enable/disable accelerometer X axis totally by stripping everything related in driver. |
|
Enable/disable accelerometer Y axis totally by stripping everything related in driver. |
|
Enable/disable accelerometer Z axis totally by stripping everything related in driver. |
|
Specify the default accelerometer full-scale range. An X value for the config represents a range of +/- X G. Valid values are 2, 4, 8 and 16. |
|
Specify the default accelerometer output data rate expressed in samples per second (Hz). Data rates supported by the chip are 0, 10, 50, 119, 238, 476, 952. |
|
Enable/disable temperature totally by stripping everything related in driver. |
|
Enable/disable gyroscope X axis totally by stripping everything related in driver. |
|
Enable/disable gyroscope Y axis totally by stripping everything related in driver. |
|
Enable/disable gyroscope Z axis totally by stripping everything related in driver. |
|
Specify the default gyroscope full-scale range. An X value for the config represents a range of +/- X degree per second. Valid values are 245, 500 and 2000. |
|
Specify the default gyroscope output data rate expressed in samples per second (Hz). Data rates supported by the chip are 0, 15, 60, 119, 238, 476, 952. |
|
Enable driver for LSM6DSL accelerometer and gyroscope sensor. |
|
Specify the default accelerometer full-scale range. An X value for the config represents a range of +/- X G. Valid values are: 0: Full Scale selected at runtime 2: +/- 2g 4: +/- 4g 8: +/- 8g 16: +/- 16g |
|
Specify the default accelerometer output data rate expressed in samples per second (Hz). 0: ODR selected at runtime 1: 12.5Hz 2: 26Hz 3: 52Hz 4: 104Hz 5: 208Hz 6: 416Hz 7: 833Hz 8: 1660Hz 9: 3330Hz 10: 6660Hz |
|
Enable/disable temperature |
|
LIS2MDL |
|
LPS22HB |
|
Specify the default gyroscope full-scale range. An X value for the config represents a range of +/- X degree per second. Valid values are: 0: Full Scale selected at runtime 125: +/- 125dps 245: +/- 245dps 500: +/- 500dps 1000: +/- 1000dps 2000: +/- 2000dps |
|
Specify the default accelerometer output data rate expressed in samples per second (Hz). 0: ODR selected at runtime 1: 12.5Hz 2: 26Hz 3: 52Hz 4: 104Hz 5: 208Hz 6: 416Hz 7: 833Hz 8: 1660Hz 9: 3330Hz 10: 6660Hz |
|
Enable/disable internal sensorhub |
|
Priority of thread used by the driver to handle interrupts. |
|
Stack size of thread used by the driver to handle interrupts. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
Enable driver for LSM6DSO accelerometer and gyroscope sensor. |
|
Specify the default accelerometer full-scale range. An X value for the config represents a range of +/- X G. Valid values are: 0: Full Scale selected at runtime 2: +/- 2g 4: +/- 4g 8: +/- 8g 16: +/- 16g |
|
Specify the default accelerometer output data rate expressed in samples per second (Hz). 0: ODR selected at runtime 1: 12.5Hz 2: 26Hz 3: 52Hz 4: 104Hz 5: 208Hz 6: 416Hz 7: 833Hz 8: 1660Hz 9: 3330Hz 10: 6660Hz |
|
Enable/disable temperature |
|
Enable HTS221 as external sensor |
|
Enable LIS2MDL as external sensor |
|
Enable LPS22HB as external sensor |
|
Enable LPS22HH as external sensor |
|
Specify the default gyroscope full-scale range. An X value for the config represents a range of +/- X degree per second. Valid values are: 0: Full Scale selected at runtime 125: +/- 125dps 250: +/- 250dps 500: +/- 500dps 1000: +/- 1000dps 2000: +/- 2000dps |
|
Specify the default accelerometer output data rate expressed in samples per second (Hz). 0: ODR selected at runtime 1: 12.5Hz 2: 26Hz 3: 52Hz 4: 104Hz 5: 208Hz 6: 416Hz 7: 833Hz 8: 1660Hz 9: 3330Hz 10: 6660Hz |
|
int1 |
|
int2 |
|
Enable/disable internal sensorhub. You can enable a maximum of two external sensors (if more than two are enabled the system would enumerate only the first two found) |
|
Priority of thread used by the driver to handle interrupts. |
|
Stack size of thread used by the driver to handle interrupts. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
Enable driver for LSM9DS0 I2C-based gyroscope sensor. |
|
2000 DPS |
|
245 DPS |
|
500 DPS |
|
Enable alteration of full-scale attribute at runtime. |
|
190 Hz |
|
380 Hz |
|
760 Hz |
|
95 Hz |
|
Enable alteration of sampling rate frequency at runtime. |
|
Specify the internal thread stack size. |
|
Enable triggers |
|
Enable data ready trigger |
|
Enable driver for LSM9DS0 I2C-based MFD sensor. |
|
Enable/disable accelerometer totally by stripping everything related in driver. |
|
Enable accelerometer X axis |
|
Enable accelerometer Y axis |
|
Enable accelerometer Z axis |
|
16G |
|
2G |
|
4G |
|
6G |
|
8G |
|
Enable alteration of accelerometer full-scale attribute at runtime. |
|
0 Hz (power down) |
|
100 Hz |
|
12.5 Hz |
|
1600 Hz |
|
200 Hz |
|
25 Hz |
|
3.125 Hz |
|
400 Hz |
|
50 Hz |
|
6.25 Hz |
|
800 Hz |
|
Enable alteration of accelerometer sampling rate attribute at runtime. |
|
Enable/disable magnetometer totally by stripping everything related in driver. |
|
12 Gauss |
|
2 Gauss |
|
4 Gauss |
|
8 Gauss |
|
Enable alteration of magnetometer full-scale attribute at runtime. |
|
100 Hz |
|
12.5 Hz |
|
25 Hz |
|
3.125 Hz |
|
50 Hz |
|
6.25 Hz |
|
Enable alteration of magnetometer sampling rate attribute at runtime. |
|
Enable/disable temperature sensor totally by stripping everything related in driver. |
|
Enable I2C-based driver for MAX17055 Fuel Gauge. This driver supports reading various sensor settings including charge level percentage, time to full/empty, design voltage, temperature and remaining capacity in mA. |
|
MAX30101 Pulse Oximeter and Heart Rate Sensor |
|
Set the ADC’s full-scale range. 0 = 7.81 pA/LSB 1 = 15.63 pA/LSB 2 = 31.25 pA/LSB 3 = 62.5 pA/LSB |
|
Set the trigger for the FIFO_A_FULL interrupt |
|
Controls the behavior of the FIFO when the FIFO becomes completely filled with data. If set, the FIFO address rolls over to zero and the FIFO continues to fill with new data. If not set, then the FIFO is not updated until FIFO_DATA is read or the WRITE/READ pointer positions are changed. |
|
Set to operate in heart rate only mode. The red LED channel is active. |
|
Set the pulse amplitude to control the LED1 (red) current. The actual measured LED current for each part can vary significantly due to the trimming methodology. 0x00 = 0.0 mA 0x01 = 0.2 mA 0x02 = 0.4 mA 0x0f = 3.1 mA 0xff = 50.0 mA |
|
Set the pulse amplitude to control the LED2 (IR) current. The actual measured LED current for each part can vary significantly due to the trimming methodology. 0x00 = 0.0 mA 0x01 = 0.2 mA 0x02 = 0.4 mA 0x0f = 3.1 mA 0xff = 50.0 mA |
|
Set the pulse amplitude to control the LED3 (green) current. The actual measured LED current for each part can vary significantly due to the trimming methodology. 0x00 = 0.0 mA 0x01 = 0.2 mA 0x02 = 0.4 mA 0x0f = 3.1 mA 0xff = 50.0 mA |
|
Set to operate in multi-LED mode. The green, red, and/or IR LED channels are active. |
|
Set which LED and pulse amplitude are active in time slot 1. 0: None (disabled) 1: LED1 (red), LED1_PA 2: LED2 (IR), LED2_PA 3: LED3 (green), LED3_PA 4: None (disabled) 5: LED1 (red), PILOT_PA 6: LED2 (IR), PILOT_PA 7: LED3 (green), PILOT_PA |
|
Set which LED and pulse amplitude are active in time slot 2. 0: None (disabled) 1: LED1 (red), LED1_PA 2: LED2 (IR), LED2_PA 3: LED3 (green), LED3_PA 4: None (disabled) 5: LED1 (red), PILOT_PA 6: LED2 (IR), PILOT_PA 7: LED3 (green), PILOT_PA |
|
Set which LED and pulse amplitude are active in time slot 3. 0: None (disabled) 1: LED1 (red), LED1_PA 2: LED2 (IR), LED2_PA 3: LED3 (green), LED3_PA 4: None (disabled) 5: LED1 (red), PILOT_PA 6: LED2 (IR), PILOT_PA 7: LED3 (green), PILOT_PA |
|
Set which LED and pulse amplitude are active in time slot 4. 0: None (disabled) 1: LED1 (red), LED1_PA 2: LED2 (IR), LED2_PA 3: LED3 (green), LED3_PA 4: None (disabled) 5: LED1 (red), PILOT_PA 6: LED2 (IR), PILOT_PA 7: LED3 (green), PILOT_PA |
|
To reduce the amount of data throughput, adjacent samples (in each individual channel) can be averaged and decimated on the chip by setting this register. Set to 0 for no averaging. 0 = 1 sample (no averaging) 1 = 2 samples 2 = 4 samples 3 = 8 samples 4 = 16 samples 5 = 32 samples 6 = 32 samples 7 = 32 samples |
|
Set to operate in SpO2 mode. The red and IR LED channels are active. |
|
Set the effective sampling rate with one sample consisting of one pulse/conversion per active LED channel. In SpO2 mode, these means one IR pulse/conversion and one red pulse/conversion per sample period. 0 = 50 Hz 1 = 100 Hz 2 = 200 Hz 3 = 400 Hz 4 = 800 Hz 5 = 1000 Hz 6 = 1600 Hz 7 = 3200 Hz |
|
Enable driver for MAX44009 light sensors. |
|
The maximum number of interrupt inputs to any aggregator in the system. |
|
This module implements a kernel device driver for the Microchip XEC series RTOS timer and provides the standard “system clock driver” interfaces. |
|
Enable driver for MCP9808 temperature sensor. |
|
MCP9808 thread priority |
|
Sensor delayed work thread stack size |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
16 MHz |
|
1 MHz |
|
250 kHz |
|
32768 Hz |
|
32 MHz |
|
4 MHz |
|
62500 Hz |
|
8 MHz |
|
Disabled |
|
If this option is set, the driver does not perform a hardware reset and the CLK_OUT frequency is not set, instead these settings are performed during the initialization of the SoC. |
|
Enable driver for the NXP MCUX Analog Comparator (ACMP). |
|
Enable trigger support for the NXP MCUX Analog Comparator (ACMP). |
|
Rocktech rk043fn02h-ct |
|
Byte alignment in the frame buffer memory pool. |
|
Maximum block size in the frame buffer memory pool. |
|
Minimum block size in the frame buffer memory pool. |
|
Number of blocks in the frame buffer memory pool. |
|
Add support for memory controllers |
|
Memory controllers initialization priority. |
|
Enable STM32 Flexible Memory Controller. |
|
Enable STM32 FMC SDRAM controller. |
|
Enable this to be able to display images and text on the 5x5 LED matrix display on the BBC micro:bit. |
|
This value specifies the maximum length of strings that can be displayed using the mb_display_string() and mb_display_print() APIs. |
|
Enable config options for modem drivers. |
|
This generic command handler uses a modem interface to process incoming data and hand it back to the modem driver via callbacks defined for: - modem responses - unsolicited messages - specified handlers for current operation To configure this layer for use, create a modem_cmd_handler_data object and pass it’s reference to modem_cmd_handler_init() along with the modem_cmd_handler reference from your modem_context object. |
|
This option sets the maximum number of parameters which may be parsed by the command handler. This is also limited by the length of the match_buf (match_buf_len) field as it needs to be large enough to hold a single line of data (ending with /r). |
|
This driver allows modem drivers to communicate with an interface using custom defined protocols. Driver doesn’t inspect received data and all aspects of received protocol data are handled by application work method provided. This driver combines abstractions for: modem interface, command handler, pin config and socket handling each of which will need to be configured. |
|
Maximum number of modem contexts to handle. For most purposes this should stay at 1. |
|
Enabling this setting will turn on VERY heavy debugging from the modem context helper. Do NOT leave on for production. |
|
Specify Access Point Name, i.e. the name to identify Internet IP GPRS cellular data context. |
|
The modem does not need any special handling etc. |
|
The GSM modem is initialized in POST_KERNEL using priority in the range 0-99. |
|
This setting is used in the AT+COPS command to set the MCC/MNO for the network connection context. This value is specific to the network provider and may need to be changed if auto is not selected. |
|
Enable GSM modems that support standard AT commands and PPP. |
|
Sets the stack size which will be used by the GSM RX thread. |
|
Use this if you have SIMCOM based modem like SIM800 etc. |
|
UART device name the modem is connected to |
|
Choose this setting to enable Sierra Wireless HL7800 LTE-M/NB-IoT modem driver. |
|
This setting is used in the AT+CGDCONT command to set the APN name for the PDP context. |
|
Enable Band 1 (2000MHz) |
|
Enable Band 10 (2100MHz) |
|
Enable Band 12 (700MHz) |
|
Enable Band 13 (700MHz) |
|
Enable Band 14 (700MHz) |
|
Enable Band 17 (700MHz) |
|
Enable Band 18 (800MHz) |
|
Enable Band 19 (800MHz) |
|
Enable Band 2 (1900MHz) |
|
Enable Band 20 (800MHz) |
|
Enable Band 25 (1900MHz) |
|
Enable Band 26 (800MHz) |
|
Enable Band 27 (800MHz) |
|
Enable Band 28 (700MHz) |
|
Enable Band 3 (1800MHz) |
|
Enable Band 4 (1700MHz) |
|
Enable Band 5 (850MHz) |
|
Enable Band 66 (1800MHz) |
|
Enable Band 8 (900MHz) |
|
Enable Band 9 (1900MHz) |
|
Choose this setting to configure which LTE bands the HL7800 modem should use. |
|
Enable LTE eDRX |
|
Half a byte in a 4-bit format. The eDRX value refers to bit 4 to 1 of octet 3 of the Extended DRX parameters information element. Default value is 81.92 seconds. |
|
Enable the ability to update the HL7800 via XMODEM by providing an update file to the update API. |
|
HL7800 device driver initialization priority. Do not mess with it unless you know what you are doing. Note that the priority needs to be lower than the net stack so that it can start before the networking sub-system. |
|
Choose this setting to enable a low power mode for the HL7800 modem |
|
Enable Power Save Mode (PSM) |
|
Requested Active Time value (T3324) to be allocated to the UE. One byte in an 8-bit format. Default value is 30 seconds. |
|
Requested extended periodic TAU (tracking area update) value (T3412) to be allocated to the UE in E-UTRAN. One byte in an 8-bit format. Default value is 1 minute. |
|
Enable LTE Cat-M1 mode during modem init. |
|
Enable LTE Cat-NB1 mode during modem init. |
|
Leave the HL7800 RAT unchanged during modem init. |
|
The number of allocated network buffers |
|
The size of the network buffers in bytes |
|
This stack is used by the HL7800 RX thread. |
|
This stack is used by the work queue to pass off net_pkt data to the rest of the network stack, letting the rx thread continue processing data. |
|
If APN doesn’t match MODEM_HL7800_APN_NAME on startup, then it will be set. |
|
To configure this layer for use, create a modem_iface_uart_data object and pass it’s reference to modem_iface_uart_init() along with the modem_iface reference from your modem_context object and the UART device name. |
|
Choose this setting to enable quectel BG9x LTE-CatM1/NB-IoT modem driver. |
|
This setting is used to set the APN name for the network connection context. This value is specific to the network provider and may need to be changed. |
|
quectel BG9X device driver initialization priority. Do not mess with it unless you know what you are doing. Note that the priority needs to be lower than the net stack so that it can start before the networking sub-system. |
|
This setting is used to set the Password for the network connection context. This value is specific to the network provider and may need to be changed. |
|
This stack is used by the quectel BG9X RX thread. |
|
This stack is used by the work queue to pass off net_pkt data to the rest of the network stack, letting the rx thread continue processing data. |
|
This setting is used to set the User name for the network connection context. This value is specific to the network provider and may need to be changed. |
|
This driver allows modem drivers to communicate over UART with custom defined protocols. Driver doesn’t inspect received data and all aspects of received protocol data are handled by application via work method provided. This driver differs from the pipe UART driver in that callbacks are executed in a different work queue and data is passed around in k_pipe structures. |
|
Maximum number of modem receiver contexts to handle. For most purposes this should stay at 1. |
|
Activate shell module that provides modem utilities like sending a command to the modem UART. |
|
Query the SIM card for the IMSI and ICCID identifiers. This can be disabled if the application does not use a SIM. |
|
This layer provides much of the groundwork for keeping track of modem “sockets” throughout their lifecycle (from the initial offload API calls through the command handler call back layers). To configure this layer for use, create a modem_socket_config object with your socket data and pass it’s reference to modem_socket_init(). |
|
As the modem indicates more data is available to be received, these values are organized into “packets”. This setting limits the maximum number of packet sizes the socket can keep track of. |
|
Choose this setting to enable u-blox SARA-R4 LTE-CatM1/NB-IoT modem driver. |
|
Enable automatic detection of the APN, based on the IMSI If the detection fails, the configured APN will be used |
|
Set a comma separated list of profiles, each containing of: <apn>=<IMSI_1> … <IMSI_n> |
|
Enable automatic detection of modem variant (SARA-R4 or SARA-U2) |
|
Enable support for SARA-R4 modem |
|
This setting is used in the AT+CGDCONT command to set the APN name for the network connection context. This value is specific to the network provider and may need to be changed. |
|
u-blox SARA-R4 device driver initialization priority. Do not mess with it unless you know what you are doing. Note that the priority needs to be lower than the net stack so that it can start before the networking sub-system. |
|
This setting is used in the AT+COPS command to set the MCC/MNO for the network connection context. This value is specific to the network provider and may need to be changed if auto is not selected. |
|
Driver name |
|
Choose this setting to use a modem GPIO pin as network indication. |
|
This setting is used to configure one of the modem’s GPIO pins as a network status indication. See the manual for the gpio ids and how they map to pin numbers. |
|
This stack is used by the u-blox SARA-R4 RX thread. |
|
This stack is used by the work queue to pass off net_pkt data to the rest of the network stack, letting the rx thread continue processing data. |
|
u-blox SARA-R4 device is configured to poll for RSSI |
|
This settings is used to configure the period of RSSI polling |
|
Enable support for SARA-U2 modem |
|
Choose this setting to enable Wistron WNC-M14A2A LTE-M modem driver. NOTE: Currently the pin settings only work with FRDM K64F shield. |
|
This setting is used in the AT%PDNSET command to set the APN name for the network connection context. Normally, don’t need to change this value. |
|
WNC-M14A2A device driver initialization priority. Do not mess with it unless you know what you are doing. Note that the priority needs to be lower than the net stack so that it can start before the networking sub-system. |
|
This stack is used by the WNCM14A2A RX thread. |
|
This stack is used by the work queue to pass off net_pkt data to the rest of the network stack, letting the rx thread continue processing data. |
|
Enable driver for MPR pressure sensor. |
|
0 to 1 |
|
0 to 15 |
|
0 to 25 |
|
0 to 30 |
|
0 to 60 |
|
0 to 100 |
|
0 to 160 |
|
0 to 1.6 |
|
0 to 250 |
|
0 to 2.5 |
|
0 to 400 |
|
0 to 600 |
|
bar |
|
kPa |
|
mbar |
|
psi |
|
A |
|
B |
|
C |
|
Enable driver for MPU6050 I2C-based six-axis motion tracking device. |
|
Magnetometer full-scale range. An X value for the config represents a range of +/- X g. Valid values are 2, 4, 8 and 16. |
|
Gyroscope full-scale range. An X value for the config represents a range of +/- X degrees/second. Valid values are 250, 500, 1000, 2000. |
|
Priority of thread used by the driver to handle interrupts. |
|
Stack size of thread used by the driver to handle interrupts. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
Enable driver for MS5607 pressure and temperature sensor. |
|
x1024 |
|
x2048 |
|
x256 |
|
x4096 |
|
x512 |
|
x1024 |
|
x2048 |
|
x256 |
|
x4096 |
|
x512 |
|
Enable driver for MS5837 pressure and temperature sensor. |
|
Multiple levels of interrupts are normally used to increase the number of addressable interrupts in a system. For example, if two levels are used, a second level interrupt aggregator would combine all interrupts routed to it into one IRQ line in the first level interrupt controller. If three levels are used, a third level aggregator combines its input interrupts into one IRQ line at the second level. The number of interrupt levels is usually determined by the hardware. (The term “aggregator” here means “interrupt controller”.) |
|
Use the host terminal (where the native_posix binary was launched) for the Zephyr console |
|
Device driver initialization priority. |
|
No current use. Kept only as there is plans to start using these drivers with the shell |
|
Zephyr’s printk messages will be directed to the host terminal stdout. |
|
This module implements a kernel device driver for the native_posix HW timer model |
|
In ms, polling period for stdin |
|
Connect this UART to its own pseudoterminal. This is the preferred option for users who want to use Zephyr’s shell. Moreover this option does not conflict with any other native_posix backend which may use the calling shell standard input/output. |
|
Connect this UART to the stdin & stdout of the calling shell/terminal which invoked the native_posix executable. This is good enough for automated testing, or when feeding from a file/pipe. Note that other, non UART messages, will also be printed to the terminal. This option should NOT be used in conjunction with NATIVE_POSIX_STDIN_CONSOLE It is strongly discouraged to try to use this option with the new shell interactively, as the default terminal configuration is NOT appropriate for interactive use. |
|
If the native_posix executable is called with the –attach_uart command line option, this will be the default command which will be run to attach a new terminal to the 1st UART. Note that this command must have one, and only one, ‘%s’ as placeholder for the pseudoterminal device name (e.g. /dev/pts/35) This is only applicable if the UART_0 is configured to use its own PTY with NATIVE_UART_0_ON_OWN_PTY. The 2nd UART will not be affected by this option. If you are using GNOME, then you can use this command string ‘gnome-terminal – screen %s’ |
|
Enable Distributed Switch Architecture support. For now it only supports Kinetics ENET driver. |
|
Net loopback driver |
|
Point-to-point (PPP) UART based driver |
|
This option sets the driver name |
|
PPP ring buffer size when passing data from RX ISR to worker thread that will pass the data to IP stack. |
|
Sets the priority of the RX workqueue thread. |
|
Sets the stack size which will be used by the PPP RX workqueue. |
|
This options sets the size of the UART buffer where data is being read to. |
|
UART device name the PPP is connected to |
|
If you have a reliable link, then it might make sense to disable this as it takes some time to verify the received packet. |
|
Enable support for Neural Network Accelerators |
|
Enable support for nrfx QSPI driver with EasyDMA. |
|
When CONFIG_FLASH_PAGE_LAYOUT is used this driver will support that API. By default the page size corresponds to the block size (65536). Other option include the sector size (4096). |
|
Device driver initialization priority. |
|
The QSPI peripheral uses DMA and cannot write data that is read from the internal flash. A non-zero value here enables a stack buffer into which data is copied to allow the write to proceed. Multiple transfers will be initiated if the data is larger than the configured limit. Must be a multiple of 4. The feature is disabled when set to 0. |
|
This option enables the Multi-Input Wake-Up Unit (MIWU) driver for NPCX family ofprocessors. This is required for GPIO, RTC, LPC/eSPI interrupt support. |
|
Enable DPPI allocator |
|
Enable PPI allocator |
|
Enable TIMER driver |
|
Enable TIMER0 instance |
|
Enable TIMER1 instance |
|
Enable TIMER2 instance |
|
Enable TIMER3 instance |
|
Enable TIMER4 instance |
|
Enable support for nrfx WDT instance 0. |
|
Enable support for nrfx WDT instance 1. |
|
This module implements a kernel device driver for the nRF Real Time Counter NRF_RTC1 and provides the standard “system clock driver” interfaces. |
|
Use nrf_rtc_timer.h API. Driver is not managing allocation of channels. |
|
The number of level 2 interrupt aggregators to support. Each aggregator can manage at most MAX_IRQ_PER_AGGREGATOR level 2 interrupts. |
|
The number of level 3 interrupt aggregators to support. Each aggregator can manage at most MAX_IRQ_PER_AGGREGATOR level 3 interrupts. |
|
Enable driver for OPT3001 light sensors. |
|
Enable LED driver for PCA9633. PCA9633 LED driver has 4 channels each with multi-programmable states. Each channel can drive up to 25 mA per LED. |
|
This option enables support for new PCI(e) drivers. |
|
This option enables PCIe Endpoint support. |
|
This option enables Broadcom iProc PCIe EP driver. |
|
Re-initialize PCIe MSI/MSIX configurations |
|
Version-2 of iProc PCIe EP controller |
|
Use Message-Signaled Interrupts where possible. With this option enabled, PCI(e) devices which support MSI will be configured (at runtime) to use them. This is typically required for PCIe devices to generate interrupts at all. |
|
MSI can support up to 32 different messages. This will enable the support of such capability so each message can get a vector assigned to it. This will require for the selected architecture to provide the necessary logic to make it work. Disable this if the vectors cannot be managed by the hardware or if none of the peripheral require this. |
|
If one or more device support MSI-X, you’ll need to enable this. If a device exposes support for both MSI-X and MSI, MSI-X will be used and MSI disabled on that device. Enable PCIE_MSI_MULTI_VECTOR if you want to support multi-vector on MSI-X as well. |
|
Enable commands for debugging PCI(e) using the built-in shell. |
|
Include PECI drivers in system config. |
|
PECI device driver initialization priority. There isn’t any critical component relying on this priority at the moment. |
|
This is an option to be enabled by individual peci driver to indicate that the driver and hardware supports interrupts. |
|
Enable the Microchip XEC PECI IO driver. |
|
Enable board pinmux driver |
|
Enable driver for ARM V2M Beetle Pin multiplexer. |
|
Enable the TI SimpleLink CC13xx / CC26xx pinmux driver. |
|
Enable driver for ESP32 Pin multiplexer. |
|
Enable driver for ARC HSDK I/O pin mux. |
|
Pinmux driver initialization priority. Pinmux driver almost certainly should be initialized before the rest of hardware devices (which may need specific pins already configured for them), and usually after generic GPIO drivers. Thus, its priority should be between KERNEL_INIT_PRIORITY_DEFAULT and KERNEL_INIT_PRIORITY_DEVICE. There are exceptions to this rule for particular boards. Don’t change this value unless you know what you are doing. |
|
Enable driver for Intel S1000 I/O multiplexer. |
|
Enable driver for the IT8XXX2 pinmux driver |
|
IT8XXX2 pinmux driver name |
|
Enable pinmux driver for NXP LPC11U6X MCUs. |
|
Enable the MCUX pinmux driver. |
|
Enable the MCUX LPC pinmux driver. |
|
Enable Port 0. |
|
Pinmux Port 0 driver name |
|
Enable Port 1. |
|
Pinmux Port 1 driver name |
|
The name of the pinmux driver. |
|
Enable support for NPCX pinmux controller driver. |
|
Enable the RV32M1 pinmux driver. |
|
Enable support for the Atmel SAM0 PORT pin multiplexer. |
|
Enable driver for the SiFive Freedom SOC pinmux driver |
|
SIFIVE pinmux 0 driver name |
|
Enable pin multiplexer for STM32 MCUs |
|
This option controls the priority of pinmux device initialization. Higher priority ensures that the device is initialized earlier in the startup cycle. Note that the pinmux device needs to be initialized after clock control device, but possibly before all other devices. If unsure, leave at default value 2 |
|
Enable the Microchip XEC pinmux driver. |
|
Platform Level Interrupt Controller provides support for external interrupt lines defined by the RISC-V SoC; |
|
Enable driver for pms7003 particulate matter sensor. |
|
This is only necessary if a ppp connection should be established with a Microsoft Windows PC. |
|
Specify a MAC address for the PPP interface in the form of six hex 8-bit chars separated by colons (e.g.: aa:33:cc:22:e2:c0). The default is an empty string, which means the code will make 00:00:5E:00:53:XX, where XX will be random. |
|
Include PS/2 drivers in system config. |
|
PS/2 device driver initialization priority. There isn’t any critical component relying on this priority at the moment. |
|
Enable the Microchip XEC PS2 IO driver. The driver also depends on the KBC 8042 keyboard controller. |
|
Enable PS2 0. |
|
Enable PS2 1. |
|
Enable options for Precision Time Protocol Clock drivers. |
|
Enable MCUX PTP clock support. |
|
Enable SAM GMAC PTP Clock support. |
|
Enable config options for PWM drivers. |
|
This option extends the Zephyr PWM API with the ability to capture PWM period/pulse widths. |
|
PWM capture filter value for channels 0 and 2. |
|
Enable support for i.MX pwm driver. |
|
This option enables the PWM LED driver for ESP32 family of processors. Say y if you wish to use PWM LED port on ESP32. |
|
Specify the device name for the PWM driver. |
|
Set high speed channels |
|
Enable channel 0 |
|
GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39. |
|
Timer source channel, allowed values: 0 - 4. |
|
Enable channel 1 |
|
GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39. |
|
Timer source channel, allowed values: 0 - 4. |
|
Enable channel 2 |
|
GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39. |
|
Timer source channel, allowed values: 0 - 4. |
|
Enable channel 3 |
|
GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39. |
|
Timer source channel, allowed values: 0 - 4. |
|
Enable channel 4 |
|
GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39. |
|
Timer source channel, allowed values: 0 - 4. |
|
Enable channel 5 |
|
GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39. |
|
Timer source channel, allowed values: 0 - 4. |
|
Enable channel 6 |
|
GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39. |
|
Timer source channel, allowed values: 0 - 4. |
|
Enable channel 7 |
|
GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39. |
|
Timer source channel, allowed values: 0 - 4. |
|
Set high speed timers |
|
Set timer 0 |
|
PWM timer precision, allowed values: 10 - 15. |
|
Set frequency |
|
Set timer 1 |
|
PWM timer precision, allowed values: 10 - 15. |
|
Set frequency |
|
Set timer 2 |
|
PWM timer precision, allowed values: 10 - 15. |
|
Set frequency |
|
Set timer 3 |
|
PWM timer precision, allowed values: 10 - 15. |
|
Set frequency |
|
Set low speed channels |
|
Enable channel 0 |
|
GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39. |
|
Timer source channel, allowed values: 0 - 4. |
|
Enable channel 1 |
|
GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39. |
|
Timer source channel, allowed values: 0 - 4. |
|
Enable channel 2 |
|
GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39. |
|
Timer source channel, allowed values: 0 - 4. |
|
Enable channel 3 |
|
GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39. |
|
Timer source channel, allowed values: 0 - 4. |
|
Enable channel 4 |
|
GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39. |
|
Timer source channel, allowed values: 0 - 4. |
|
Enable channel 5 |
|
GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39. |
|
Timer source channel, allowed values: 0 - 4. |
|
Enable channel 6 |
|
GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39. |
|
Timer source channel, allowed values: 0 - 4. |
|
Enable channel 7 |
|
GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39. |
|
Timer source channel, allowed values: 0 - 4. |
|
Set low speed timers |
|
Set timer 0 |
|
PWM timer precision, allowed values: 10 - 15. |
|
Set frequency |
|
Set timer 1 |
|
PWM timer precision, allowed values: 10 - 15. |
|
Set frequency |
|
Set timer 2 |
|
PWM timer precision, allowed values: 10 - 15. |
|
Set frequency |
|
Set timer 3 |
|
PWM timer precision, allowed values: 10 - 15. |
|
Set frequency |
|
Enable support for LiteX PWM driver |
|
PWM device driver initialization priority. |
|
Enable mcux pwm driver. |
|
Enable support for mcux ftm pwm driver. |
|
Enable the MCUX Pulse Width Timer (PWT) PWM capture driver. |
|
Enable the MCUX TPM PWM driver. |
|
Enable support for NPCX PWM driver. |
|
Enable driver to utilize PWM on the Nordic Semiconductor nRF5x series. When used with HF timer it provides up to 3 pins, utilizing two PPI channels per pin and one GPIOTE config per pin. When used with RTC it provides up to 3 pins, utilizing three PPI channels per pin and one GPIOTE config per pin. |
|
Enable support for nrfx Hardware PWM driver for nRF52 MCU series. |
|
Loop count for PWM Software Reset when disabling PWM channel. |
|
Enable the RV32M1 TPM PWM driver. |
|
Enable PWM driver for Atmel SAM MCUs. |
|
Enable PWM driver for Atmel SAM0 MCUs using the TCC timer/counter. |
|
Enable the PWM related shell commands. |
|
Enable the PWM driver for the SiFive Freedom platform |
|
SiFive PWM Driver Initialization Priority |
|
This option enables the PWM driver for STM32 family of processors. Say y if you wish to use PWM port on STM32 MCU. |
|
Enable driver to utilize PWM on the Microchip XEC IP block. |
|
Enable PWM support for the Xilinx AXI Timer v2.0 IP. |
|
Enable support for nrfx QDEC driver for nRF MCU series. |
|
Emit console messages to a RAM buffer “ram_console” which can be examined at runtime with a debugger. Useful in board bring-up if there aren’t any working serial drivers. |
|
Size of the RAM console buffer. Messages will wrap around if the length is exceeded. |
|
Include drivers for current/voltage regulators in system config |
|
Enable the driver for GPIO-controlled regulators |
|
Device driver initialization priority |
|
This module implements a kernel device driver for the generic RISCV machine timer driver. It provides the standard “system clock driver” interfaces. |
|
Emit console messages to a RAM buffer that is then read by the Segger J-Link software and displayed on a computer in real-time. Requires support for Segger J-Link on the companion IC onboard. |
|
Number of TX retries before dropping the byte and assuming that RTT session is inactive. |
|
Sleep period between TX retry attempts. During RTT session, host pulls data periodically. Period starts from 1-2 milliseconds and can be increased if traffic on RTT increases (also from host to device). In case of heavy traffic data can be lost and it may be necessary to increase delay or number of retries. |
|
If enabled RTT console will busy wait between TX retries when console assumes that RTT session is active. In case of heavy traffic data can be lost and it may be necessary to increase delay or number of retries. |
|
Select this option to enable support for the RV32M1 INTMUX driver. This provides a level 2 interrupt controller for the SoC. The INTMUX peripheral combines level 2 interrupts into eight channels; each channel has its own level 1 interrupt to the core. |
|
Enable support for INTMUX channel 0. |
|
Enable support for INTMUX channel 1. |
|
Enable support for INTMUX channel 2. |
|
Enable support for INTMUX channel 3. |
|
Enable support for INTMUX channel 4. |
|
Enable support for INTMUX channel 5. |
|
Enable support for INTMUX channel 6. |
|
Enable support for INTMUX channel 7. |
|
Boot time initialization priority for INTMUX driver. Don’t change the default unless you know what you are doing. |
|
This module implements a kernel device driver for using the LPTMR peripheral as the system clock. It provides the standard “system clock driver” interfaces. |
|
Enable EIC driver for SAM0 series of devices. This is required for GPIO interrupt support. |
|
This module implements a kernel device driver for the Atmel SAM0 series Real Time Counter and provides the standard “system clock driver” interfaces. |
|
Enable SDL based emulated display compliant with display driver API. |
|
ARGB 8888 |
|
BGR 565 |
|
Mono Black=0 |
|
Mono Black=1 |
|
RGB 565 |
|
RGB 888 |
|
SDL display device name |
|
X resolution for SDL display |
|
Y resolution for SDL display |
|
SDL kscan device name |
|
Size of the buffer for terminal input of target, from host |
|
Size of the buffer for terminal output of target, up to host |
|
Maximum number of down-buffers |
|
Maximum number of up-buffers |
|
Use a simple byte-loop instead of standard memcpy |
|
Block: Wait until there is space in the buffer. |
|
Skip. Do not block, output nothing. |
|
Trim: Do not block, output as much as fits. |
|
Size of buffer for RTT printf to bulk-send chars via RTT |
|
Place RTT data in the DTCM linker section |
|
Place RTT data in the default linker section |
|
Enable this option to use semihosting for console. Semihosting is a mechanism that enables code running on an ARM target to communicate and use the Input/Output facilities on a host computer that is running a debugger. Additional information can be found in: https://developer.arm.com/docs/dui0471/k/what-is-semihosting/what-is-semihosting This option is compatible with hardware and with QEMU, through the (automatic) use of the -semihosting-config switch when invoking it. |
|
Include sensor drivers in system config |
|
Sensor initialization priority. |
|
This shell provides access to basic sensor data. |
|
This enables the ‘battery’ command which reports charging information in a convenient format. It makes use of a fuel gauge to read its information. |
|
Enable options for serial drivers. |
|
This is an option to be enabled by individual serial driver to signal that there is a serial driver. This is being used by other drivers which are dependent on serial. |
|
This is an option to be enabled by individual serial driver to signal that the driver and hardware supports async operation. |
|
This is an option to be enabled by individual serial driver to signal that the driver and hardware supports interrupts. |
|
Include shared interrupt support in system. Shared interrupt support is NOT required in most systems. If in doubt answer no. |
|
Provide an instance of the shared interrupt driver when system configuration requires that multiple devices share an interrupt. |
|
Provide an instance of the shared interrupt driver when system configuration requires that multiple devices share an interrupt. |
|
Shared IRQ are initialized on POST_KERNEL init level. They have to be initialized before any device that uses them. |
|
Configures the maximum number of clients allowed per shared instance of the shared interrupt driver. To conserve RAM set this value to the lowest practical value. |
|
Enable driver for SHT3xD temperature and humidity sensors. |
|
0.5 |
|
1 |
|
10 |
|
2 |
|
4 |
|
periodic data acquisition |
|
high |
|
low |
|
medium |
|
single shot |
|
Priority of thread used by the driver to handle interrupts. |
|
Stack size of thread used by the driver to handle interrupts. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
Enable I2C-based driver for Si7006 Temperature and Humidity Sensor. |
|
Enable I2C-based driver for Si7055 Temperature Sensor. |
|
Validates the additional checksum byte for temperature measurements. |
|
Enable driver for SI7060 temperature sensors. |
|
If enabled, SPI 0 is reserved for accessing the SPI flash ROM and a driver interface won’t be instantiated for SPI 0. Beware disabling this option on HiFive 1! The SPI flash ROM is where the program is stored, and if this driver initializes the interface for peripheral control the FE310 will crash on boot. |
|
SLIP driver |
|
This option sets the driver name |
|
Specify a MAC address for the SLIP interface in the form of six hex 8-bit chars separated by colons (e.g.: aa:33:cc:22:e2:c0). The default is an empty string, which means the code will make 00:00:5E:00:53:XX, where XX will be random. |
|
This option enables statistics support for SLIP driver. |
|
In TAP the Ethernet frames are transferred over SLIP. |
|
Enable GPIO-based driver for SM351LT magnetoresistive sensor. |
|
Priority of thread used by the driver to handle interrupts. |
|
Stack size of thread used by the driver to handle interrupts. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
Enable Silicon Labs Gecko series internal flash driver. |
|
Enables the LPC IAP flash shim driver. WARNING: This driver will disable the system interrupts for the duration of the flash erase/write operations. This will have an impact on the overall system performance - whether this is acceptable or not will depend on the use case. |
|
Enables the MCUX flash shim driver. WARNING: This driver will disable the system interrupts for the duration of the flash erase/write operations. This will have an impact on the overall system performance - whether this is acceptable or not will depend on the use case. |
|
Enables the Nios-II QSPI flash driver. |
|
Specify the device name for the QSPI flash driver. |
|
Enables Nordic Semiconductor nRF flash driver. |
|
When this option is enabled writing chunks less than minimal write block size parameter (imposed by manufacturer) is possible but operation is more complex and requires basic user knowledge about NVMC controller. |
|
Enable partial erase feature. Partial erase is performed in time slices instead of blocking MCU, for the time it is needed to complete operation over given area. This allows interrupting flash erase between operations to perform other task by MCU. This feature may also be used for better syncing flash erase operations, when compiled with SOC_FLASH_NRF_RADIO_SYNC_TICKER, with Bluetooth. |
|
This is maximum time, in ms, that NVMC will use to erase part of Flash, before stopping to let CPU resume operation. Minimal timeout is 2ms maximum should not exceed half of FLASH_PAGE_ERASE_MAX_TIME_US im ms. |
|
disable synchronization between flash memory driver and radio. |
|
Enable synchronization between flash memory driver and radio using BLE LL controller ticker API. |
|
Enable operations on UICR. Once enabled UICR are written or read as ordinary flash memory. Erase is possible for whole UICR at once. |
|
Enables the RV32M1 flash shim driver. WARNING: This driver will disable the system interrupts for the duration of the flash erase/write operations. This will have an impact on the overall system performance - whether this is acceptable or not will depend on the use case. |
|
Enable the Atmel SAM series internal flash driver. |
|
Enable the Atmel SAM0 series internal flash driver. |
|
Emulate a device with byte-sized pages by doing a read/modify/erase/write. |
|
Enable STM32F0x, STM32F1x, STM32F3x, STM32F4x, STM32F7x, STM32L0x, STM32L1x, STM32L4x, STM32WBx, STM32G0x, STM32G4x or STM3H7x series flash driver. |
|
Enable the generic backend for the STM32 flash driver. |
|
Allow enabling the nRF SPI Master with EasyDMA, despite Product Anomaly Notice 58 (SPIM: An additional byte is clocked out when RXD.MAXCNT == 1 and TXD.MAXCNT <= 1). Without this override, the SPI Master is only available without EasyDMA. Note that the ‘SPIM’ and ‘SPIS’ drivers use EasyDMA, while the ‘SPI’ driver does not. Use this option ONLY if you are certain that transactions with RXD.MAXCNT == 1 and TXD.MAXCNT <= 1 will NOT be executed. |
|
Enable support for the SPI hardware bus. |
|
Enable SPI controller port 0. |
|
Over-read character. Character clocked out after an over-read of the transmit buffer. |
|
Enable nRF SPI Master without EasyDMA on port 0. |
|
Enable nRF SPI Master with EasyDMA on port 0. |
|
Enable nRF SPI Slave with EasyDMA on port 0. Due to hardware limitations the implementation supports only simple buffers (consisting of one part) located in RAM. |
|
This sets the supported operation modes at runtime, by the SPI port 0, where: 1 is MASTER mode only (default) 2 is SLAVE mode only 3 is both modes are available. |
|
Enable SPI controller port 1. |
|
Over-read character. Character clocked out after an over-read of the transmit buffer. |
|
Enable nRF SPI Master without EasyDMA on port 1. |
|
Enable nRF SPI Master with EasyDMA on port 1. |
|
Enable nRF SPI Slave with EasyDMA on port 1. Due to hardware limitations the implementation supports only simple buffers (consisting of one part) located in RAM. |
|
This sets the supported operation modes at runtime, by the SPI port 1, where: 1 is MASTER mode only (default) 2 is SLAVE mode only 3 is both modes are available. |
|
Enable SPI controller port 2. |
|
Over-read character. Character clocked out after an over-read of the transmit buffer. |
|
Enable nRF SPI Master without EasyDMA on port 2. |
|
Enable nRF SPI Master with EasyDMA on port 2. |
|
Enable nRF SPI Slave with EasyDMA on port 2. Due to hardware limitations the implementation supports only simple buffers (consisting of one part) located in RAM. |
|
This sets the supported operation modes at runtime, by the SPI port 2, where: 1 is MASTER mode only (default) 2 is SLAVE mode only 3 is both modes are available. |
|
Enable SPI controller port 3. |
|
Over-read character. Character clocked out after an over-read of the transmit buffer. |
|
Number of 64 MHz clock cycles (15.625 ns) delay from the sampling edge of SCK (leading or trailing, depending on the CPHA setting used) until the input serial data on MISO is actually sampled. |
|
Enable nRF SPI Master with EasyDMA on port 3. |
|
Enable nRF SPI Slave with EasyDMA on port 3. Due to hardware limitations the implementation supports only simple buffers (consisting of one part) located in RAM. |
|
This sets the supported operation modes at runtime, by the SPI port 3, where: 1 is MASTER mode only (default) 2 is SLAVE mode only 3 is both modes are available. |
|
Enable SPI controller port 4. |
|
Over-read character. Character clocked out after an over-read of the transmit buffer. |
|
Number of 64 MHz clock cycles (15.625 ns) delay from the sampling edge of SCK (leading or trailing, depending on the CPHA setting used) until the input serial data on MISO is actually sampled. |
|
Enable nRF SPI Master with EasyDMA on port 4. |
|
This sets the supported operation modes at runtime, by the SPI port 4, where: 1 is MASTER mode only (default) 2 is SLAVE mode only 3 is both modes are available. |
|
Enable SPI controller port 5. |
|
This sets the supported operation modes at runtime, by the SPI port 5, where: 1 is MASTER mode only (default) 2 is SLAVE mode only 3 is both modes are available. |
|
Enable SPI controller port 6. |
|
This sets the supported operation modes at runtime, by the SPI port 6, where: 1 is MASTER mode only (default) 2 is SLAVE mode only 3 is both modes are available. |
|
Enable SPI controller port 7. |
|
This sets the supported operation modes at runtime, by the SPI port 7, where: 1 is MASTER mode only (default) 2 is SLAVE mode only 3 is both modes are available. |
|
Enable SPI controller port 8. |
|
This sets the supported operation modes at runtime, by the SPI port 8, where: 1 is MASTER mode only (default) 2 is SLAVE mode only 3 is both modes are available. |
|
This option enables the asynchronous API calls. |
|
Enable support for the TI SimpleLink CC13xx / CC26xx SPI peripheral |
|
Enable support for Designware’s SPI controllers. |
|
In some case, e.g. ARC HS Development kit, the peripheral space of DesignWare SPI only allows word access, byte access will raise exception. |
|
SPI IP block registers are part of user extended auxiliary registers and thus their access is different than memory mapped registers. |
|
Corresponds to the SSI_TX_FIFO_DEPTH and SSI_RX_FIFO_DEPTH of the DesignWare Synchronous Serial Interface. Depth ranges from 2-256. |
|
Enable clock gating |
|
Clock controller’s subsystem |
|
Only one line is used to trigger interrupts: RX, TX and ERROR interrupt go all through that line, undifferentiated. |
|
Enable clock gating |
|
Clock controller’s subsystem |
|
Single interrupt line for all interrupts |
|
Enable clock gating |
|
Clock controller’s subsystem |
|
Only one line is used to trigger interrupts: RX, TX and ERROR interrupt go all through that line, undifferentiated. |
|
Enable clock gating |
|
Clock controller’s subsystem |
|
Only one line is used to trigger interrupts: RX, TX and ERROR interrupt go all through that line, undifferentiated. |
|
Enable the SPI emulator driver. This is a fake driver in that it does not talk to real hardware. Instead it talks to emulation drivers that pretend to be devices on the emulated SPI bus. It is used for testing drivers for SPI devices. |
|
This driver can handle several instances of AT45 family chips that are enabled by specifying devicetree nodes with the “compatible” property set to “atmel,at45” and other required properties like JEDEC ID, chip capacity, block and page size etc. configured accordingly. The driver is only capable of using “power of 2” binary page sizes in those chips and at initialization configures them to work in that mode (unless it is already done). |
|
Device driver initialization priority. SPI driver needs to be initialized before this one. |
|
Use the Read-Modify-Write command (opcode 0x58) instead of the default Main Memory Program without Built-In Erase (opcode 0x02). This allows writing of data without prior erasing of corresponding pages. |
|
Enable the SPI peripherals on Gecko |
|
Device driver initialization priority. |
|
Enable the SPI peripherals on LiteX |
|
Enable support for mcux spi driver. |
|
Enable support for mcux flexcomm spi driver. |
|
Enable the SPI DMA mode for SPI instances that enable dma channels in their device tree node. |
|
Enable support for mcux spi driver. |
|
SPI NOR Flash |
|
This is the wait delay (in us) to allow for CS switching to take effect |
|
When CONFIG_FLASH_PAGE_LAYOUT is used this driver will support that API. By default the page size corresponds to the block size (65536). Other options include the 32K-byte erase size (32768), the sector size (4096), or any non-zero multiple of the sector size. |
|
Where supported deep power-down mode can reduce current draw to as little as 0.1% of standby current. However it takes some milliseconds to enter and exit from this mode. Select this option for applications where device power management is not enabled, the flash remains inactive for long periods, and when used the impact of waiting for mode enter and exit delays is acceptable. |
|
Device driver initialization priority. Device is connected to SPI bus, it has to be initialized after SPI driver. |
|
The JESD216 Basic Flash Parameters table must be provided in the sfdp-bfp property in devicetree. The size and jedec-id properties are also required. |
|
Synthesize a minimal configuration assuming 256 By page size and standard 4 KiBy and 64 KiBy erase instructions. Requires the size and jedec-id properties in the devicetree jedec,spi-nor node. |
|
Read all flash device characteristics from the device at runtime. This option is the most flexible as it should provide functionality for all supported JESD216-compatible devices. |
|
Enable support for nrfx SPI drivers for nRF MCU series. |
|
SPIM peripherals cannot transmit data directly from flash. Therefore, a buffer in RAM needs to be provided for each instance of SPI driver using SPIM peripheral, so that the driver can copy there a chunk of data from flash and transmit it. The size is specified in bytes. A size of 0 means that this feature should be disabled, and the application must then take care of not supplying buffers located in flash to the driver, otherwise such transfers will fail. |
|
Enable the Simple SPI controller |
|
Enable the RV32M1 LPSPI driver. |
|
Enable support for the SAM SPI driver. |
|
Enable support for the SAM0 SERCOM SPI driver. |
|
Enable the SPI peripherals on SiFive Freedom processors |
|
Enables Driver SPI slave operations. Slave support depends on the driver and the hardware it runs on. |
|
Enable SPI support on the STM32 family of processors. |
|
Enable the SPI DMA mode for SPI instances that enable dma channels in their device tree node. |
|
Enable Interrupt support for the SPI Driver of STM32 family. |
|
Use Slave Select pin instead of software Slave Select. |
|
Enable support for the Microchip XEC QMSPI driver. |
|
Enable Xilinx AXI Quad SPI v3.2 driver. |
|
Enable driver for SSD1306 display driver. |
|
Default SSD1306 controller |
|
SSD16XX default contrast. |
|
SSD16XX reverse video mode. |
|
Enable SH1106 compatible mode |
|
Enable driver for SSD16XX compatible controller. |
|
Enable driver for ST7789V display driver. |
|
RGB565 |
|
RGB888 |
|
LPTIM clock value |
|
Use LSE as LPTIM clock |
|
Use LSI as LPTIM clock |
|
LPTIM AutoReload value |
|
This module implements a kernel device driver for the LowPower Timer and provides the standard “system clock driver” interfaces. |
|
Enable driver for STTS751 I2C-based temperature sensor. |
|
Sensor output data rate expressed in conversions per second. Data rates supported by the chip are: 0: 1 conv every 16 sec 1: 1 conv every 8 sec 2: 1 conv every 4 sec 3: 1 conv every 2 sec 4: 1 conv every sec 5: 2 convs every sec 6: 4 convs every sec 7: 8 convs every sec 8: 16 convs every sec 9: 32 convs every sec |
|
HIGH temperature threshold to trigger an alarm |
|
LOW temperature threshold to trigger an alarm |
|
Priority of thread used by the driver to handle interrupts. |
|
Stack size of thread used by the driver to handle interrupts. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
Programmable Interrupt Controller for the SweRV EH1 RISC-V CPU; |
|
Enable driver for SX9500 I2C-based SAR proximity sensor. |
|
The SX9500 offers 4 separate proximity channels. Choose which one you are using. Valid numbers are 0 to 3. |
|
Thread priority |
|
Sensor delayed work thread stack size |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
This option enables the sys_clock_disable() API in the kernel. It is needed by some subsystems (which will automatically select it), but is rarely needed by applications. |
|
This options can be used to set a specific initialization priority value for the system clock driver. As driver initialization might need the clock to be running already, you should let the default value as it is (0). |
|
System clock source is initiated but does not wait for clock readiness. When this option is picked, system clock may not be ready when code relying on kernel API is executed. Requested timeouts will be prolonged by the remaining startup time. |
|
When true, the timer driver is not required to maintain a correct system uptime count when the system enters idle. Some platforms may take advantage of this to reduce the overhead from regular interrupts required to handle counter wraparound conditions. |
|
System clock source initialization waits until clock is available. In some systems, clock initially runs from less accurate source which has faster startup time and then seamlessly switches to the target clock source when it is ready. When this option is picked, system clock is available after system clock driver initialization but it may be less accurate. Option is equivalent to waiting for stability if clock source does not have intermediate state. |
|
System clock source initialization waits until clock is stable. When this option is picked, system clock is available and stable after system clock driver initialization. |
|
Enable the Microchip XEC tachometer sensor. |
|
Configure 2 tach edges or 1/2 tach period |
|
Configure 3 tach edges or 1 tach period |
|
Configure 5 tach edges or 2 tach periods |
|
Configure 9 tach edges or 4 tach periods |
|
Enable driver for NXP Kinetis temperature sensor. |
|
Enable weighted average digital filtering of the ADC readings as per NXP AN3031. |
|
ADC oversampling to use for the temperature sensor and bandgap voltage readings. Oversampling can help in providing more stable readings. |
|
ADC resolution to use for the temperature sensor and bandgap voltage readings. |
|
Enable driver for nRF5 temperature sensor. |
|
This option can be enabled to force an alternative implementation of the temperature sensor driver. |
|
Enable driver for the TH02 temperature sensor. |
|
Timer drivers should select this flag if they are capable of supporting tickless operation. That is, a call to z_clock_set_timeout() with a number of ticks greater than one should be expected not to produce a call to z_clock_announce() (really, not to produce an interrupt at all) until the specified expiration. |
|
The dualtimer (DTMR) present in the platform is used as a timer. This option enables the support for the timer. |
|
The drivers select this option automatically when needed. Do not modify this unless you have a very good reason for it. |
|
The timers (TMR) present in the platform are used as timers. This option enables the support for the timers. |
|
Enable driver for TI temperature and humidity sensors. |
|
Enable driver for TMP007 infrared thermopile sensors. |
|
Priority of thread used by the driver to handle interrupts. |
|
Stack size of thread used by the driver to handle interrupts. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
Enable the driver for Texas Instruments TMP112 High-Accuracy Digital Temperature Sensors. The TMP102 is compatible with the TMP112 but is less accurate and has been successfully tested with this driver. |
|
Enable driver for TMP116 and TMP117 temperature sensors. |
|
This option enables UART Asynchronous API support on port 0. |
|
When enabled, polling out does not trigger interrupt which stops TX. Feature uses a PPI channel. |
|
If enabled, the driver will configure the GPIOs used by the uart to their default configuration when device is powered down. The GPIOs will be configured back to correct state when UART is powered up. |
|
This option enables UART interrupt support on port 0. |
|
If default driver uses interrupts to count incoming bytes, it is possible that with higher speeds and/or high cpu load some data can be lost. It is recommended to use hardware byte counting in such scenarios. Hardware RX byte counting requires timer instance and one PPI channel |
|
Timer instance |
|
Enable parity bit. |
|
Size of the transmit buffer for API function: fifo_fill. This value is limited by range of TXD.MAXCNT register for particular SoC. |
|
Enable nRF UART without EasyDMA on port 0. |
|
Enable nRF UART with EasyDMA on port 0. |
|
This option enables UART Asynchronous API support on port 1. |
|
When enabled, polling out does not trigger interrupt which stops TX. Feature uses a PPI channel. |
|
If enabled, the driver will configure the GPIOs used by the uart to their default configuration when device is powered down. The GPIOs will be configured back to correct state when UART is powered up. |
|
This option enables UART interrupt support on port 1. |
|
If default driver uses interrupts to count incoming bytes, it is possible that with higher speeds and/or high cpu load some data can be lost. It is recommended to use hardware byte counting in such scenarios. Hardware RX byte counting requires timer instance and one PPI channel |
|
Timer instance |
|
Enable parity bit. |
|
Size of the transmit buffer for API function: fifo_fill. This value is limited by range of TXD.MAXCNT register for particular SoC. |
|
Enable nRF UART with EasyDMA on port 1. |
|
This option enables UART Asynchronous API support on port 2. |
|
When enabled, polling out does not trigger interrupt which stops TX. Feature uses a PPI channel. |
|
If enabled, the driver will configure the GPIOs used by the uart to their default configuration when device is powered down. The GPIOs will be configured back to correct state when UART is powered up. |
|
This option enables UART interrupt support on port 2. |
|
If default driver uses interrupts to count incoming bytes, it is possible that with higher speeds and/or high cpu load some data can be lost. It is recommended to use hardware byte counting in such scenarios. Hardware RX byte counting requires timer instance and one PPI channel |
|
Timer instance |
|
Enable parity bit. |
|
Size of the transmit buffer for API function: fifo_fill. This value is limited by range of TXD.MAXCNT register for particular SoC. |
|
Enable nRF UART with EasyDMA on port 2. |
|
This option enables UART Asynchronous API support on port 3. |
|
When enabled, polling out does not trigger interrupt which stops TX. Feature uses a PPI channel. |
|
If enabled, the driver will configure the GPIOs used by the uart to their default configuration when device is powered down. The GPIOs will be configured back to correct state when UART is powered up. |
|
This option enables UART interrupt support on port 3. |
|
If default driver uses interrupts to count incoming bytes, it is possible that with higher speeds and/or high cpu load some data can be lost. It is recommended to use hardware byte counting in such scenarios. Hardware RX byte counting requires timer instance and one PPI channel |
|
Timer instance |
|
Enable parity bit. |
|
Size of the transmit buffer for API function: fifo_fill. This value is limited by range of TXD.MAXCNT register for particular SoC. |
|
Enable nRF UART with EasyDMA on port 3. |
|
Enable the Altera JTAG UART driver, built in to many Nios II CPU designs. |
|
This option enables the APBUART driver for LEON processors. |
|
This option enables new asynchronous UART API. |
|
Enable the TI SimpleLink CC13xx / CC26xx UART driver. |
|
This option enables the CC32XX UART driver, for UART_0. |
|
This option enables the UART driver for ARM CMSDK APB UART. |
|
Enable this option to use one UART for console. Make sure CONFIG_UART_CONSOLE_ON_DEV_NAME is also set correctly. |
|
This option allows a debug server agent such as GDB to take over the handling of traffic that goes through the console logic. The debug server looks at characters received and decides to handle them itself if they are some sort of control characters, or let the regular console code handle them if they are of no special significance to it. |
|
Device driver initialization priority. Console has to be initialized after the UART driver it uses. |
|
Enables the UART console to receive mcumgr frames for image upgrade and device management. When enabled, the UART console does not process mcumgr frames, but it hands them up to a higher level module (e.g., the shell). If unset, incoming mcumgr frames are dropped. |
|
This option specifies the name of UART device to be used for UART console. |
|
This enables the API to send extra commands to drivers. This allows drivers to expose hardware specific functions. Says no if not sure. |
|
Enable the ESP32 UART using ROM routines. |
|
Enable the Gecko uart driver. |
|
This option enables the UART driver for NXP i.MX7 family processors. |
|
This option enables interrupt support for UART allowing console input and other UART based drivers. |
|
This enables the API for apps to control the serial line, such as baud rate, CTS and RTS. Implementation is up to individual driver. Says no if not sure. |
|
This option enables LiteUART serial driver. |
|
Enable UART driver for LPC11U6X series |
|
Enable the mcumgr UART driver. This driver allows the application to communicate over UART using the mcumgr protocol for image upgrade and device management. The driver doesn’t inspect received data (as contrary to console UART driver) and all aspects of received protocol data are handled by an application provided callback. |
|
This option specifies the name of UART device to be used for mcumgr UART. |
|
Specifies the number of the mcumgr UART receive buffers. Receive buffers hold received mcumgr fragments prior to reassembly. This setting’s value must satisfy the following relation: UART_MCUMGR_RX_BUF_COUNT * UART_MCUMGR_RX_BUF_SIZE >= MCUMGR_SMP_UART_MTU |
|
Specifies the size of the mcumgr UART receive buffer, in bytes. This value must be large enough to accommodate any line sent by an mcumgr client. |
|
Enable the MCUX uart driver. |
|
Enable the MCUX USART driver. |
|
Enable the MCUX IUART driver. |
|
Enable the MCUX LPSCI driver. |
|
Enable the MCUX LPUART driver. |
|
This option enables the Mi-V serial driver. |
|
This option enables the MSP432P4XX UART driver, for UART_0. |
|
Enable this option to create UART muxer that run over a physical UART. The GSM 07.10 muxing protocol is used to separate the data between these muxed UARTs. |
|
Number of instances of UART muxes. Default value is set by maximum number of DLCIs (Data Link Connection Identifiers) configured in the system. |
|
Device name template for the UART mux Devices. First device would have name $(UART_MUX_DEVICE_NAME)_0, etc. User will access muxed UART using this name. |
|
Device driver initialization priority. UART mux has to be initialized after the UART driver it uses. |
|
Tells how many real UART devices there are. Typically there is only one UART and the muxed UARTs are run on top of that. If you have two modems for example, then you would need to increase this to two. |
|
UART mux ring buffer size when passing data from RX ISR to worker thread that will do the unmuxing. |
|
Sets the priority of the RX workqueue thread. |
|
Sets the stack size which will be used by the PPP RX workqueue. |
|
Size of the temporary RX buffer in receiving ISR. |
|
As there might be lot of debug output printed, only enable this if really needed. |
|
This enables a UART driver for the POSIX ARCH with up to 2 UARTs. For the first UART port, the driver can be configured to either connect to the terminal from which native_posix was run, or into one dedicated pseudoterminal for that UART. |
|
Useful if you need to have another serial connection to host. This is used for example in PPP (Point-to-Point Protocol) implementation. |
|
This is the device name for UART, and is included in the device struct. |
|
When this option is selected a new command line switch is provided:
|
|
Enable support for NPCX UART driver. |
|
Enable support for nrfx UART drivers for nRF MCU series. Peripherals with the same instance ID cannot be used together, e.g. UART_0 and UARTE_0. |
|
This option enables the NS16550 serial driver. This driver can be used for the serial hardware available on x86 boards. |
|
In some case, e.g. ARC HS Development kit, the peripheral space of ns 16550 (DesignWare UART) only allows word access, byte access will raise exception. |
|
This enables the API for apps to send commands to driver. Says n if not sure. |
|
This enables the API for apps to control the serial line, such as CTS and RTS. Says n if not sure. |
|
The maximum number of supported driver instances in device tree. |
|
This enables support for 64-bytes FIFO and automatic hardware flow control if UART controller is 16750. |
|
This option enables the UART driver for Nuvoton Numicro family of processors. Say y to use serial port on Nuvoton MCU. |
|
Enable pipe UART driver. This driver allows application to communicate over UART with custom defined protocol. Driver doesn’t inspect received data (as contrary to console UART driver) and all aspects of received protocol data are handled by application provided callback. |
|
This option specifies the name of UART device to be used for pipe UART. |
|
This option enables the UART driver for the PL011 |
|
Build the driver to utilize UART controller Port 0. |
|
Build the driver to utilize UART controller Port 1. |
|
Enable SBSA mode for PL011 driver. SBSA stands for Server Based System Architecture. This specification among other things defines simplified UART interface which is subset of PL011 interface. |
|
This option enables the UART driver for PSoC6 family of processors. |
|
Enable support for UART_5 on port 5 in the driver. |
|
Enable support for UART_6 on port 12 in the driver. |
|
This option enables access RTT channel as UART device. |
|
Enable UART on (default) RTT channel 0. Default channel has to be configured in non-blocking skip mode. |
|
Enable UART on RTT channel 1 |
|
Enable UART on RTT channel 2 |
|
Enable UART on RTT channel 3 |
|
Enable the RV32M1 LPUART driver. |
|
Enable UART 0. |
|
Enable UART 1. |
|
Enable UART 2. |
|
Enable UART 3. |
|
This option enables the UARTx driver for Atmel SAM MCUs. |
|
This option enables the SERCOMx USART driver for Atmel SAM0 MCUs. |
|
This option enables the SiFive Freedom serial driver. |
|
This tells the driver to configure the UART port at boot, depending on the additional configure options below. |
|
Port 0 RX Threshold at which the RX FIFO interrupt triggers. |
|
Port 0 TX Threshold at which the TX FIFO interrupt triggers. |
|
This tells the driver to configure the UART port at boot, depending on the additional configure options below. |
|
Port 1 RX Threshold at which the RX FIFO interrupt triggers. |
|
Port 1 TX Threshold at which the TX FIFO interrupt triggers. |
|
This option enables the Stellaris serial driver. This specific driver can be used for the serial hardware available at the Texas Instrument LM3S6965 board. |
|
This tells the driver to configure the UART port at boot, depending on the additional configure options below. |
|
This tells the driver to configure the UART port at boot, depending on the additional configure options below. |
|
This tells the driver to configure the UART port at boot, depending on the additional configure options below. |
|
This option enables the UART driver for STM32 family of processors. Say y if you wish to use serial port on STM32 MCU. |
|
This option enables the UART driver for Xilinx MPSoC platforms. |
|
This option enables the UART driver for Xilinx UART Lite IP. |
|
This option enables the XMC4XX UART driver, for UART_0. |
|
This option enables the USARTx driver for Atmel SAM MCUs. |
|
Enable USB drivers. |
|
Kinetis and RT EHCI USB Device Controller Driver. |
|
SAM family USB HS device controller Driver. |
|
SAM0 family USB device controller Driver. |
|
Enable USB support on the STM32 F0, F1, F2, F3, F4, F7, L0, L4 and G4 family of processors. |
|
Say Y if your board uses USB DISCONNECT pin to enable the pull-up resistor on USB DP. |
|
Designware USB Device Controller Driver. |
|
Indicates whether or not USB specification version 2.0 is supported |
|
Kinetis USB Device Controller Driver. |
|
Native Posix USB Device Controller Driver. |
|
nRF USB Device Controller Driver |
|
Size of the driver’s internal event queue. Required size will depend on number of endpoints (class instances) in use. |
|
Size of the stack for the work queue thread that is used in the driver for handling the events from the USBD ISR, i.e. executing endpoint callbacks and providing proper notifications to the USB device stack. |
|
Enable this option to use the USB UART for console output. The output can be viewed from the USB host via /dev/ttyACM* port. Note that console inputs from the USB UART are not functional yet. Also since the USB layer currently doesn’t support multiple interfaces, this shouldn’t be selected in conjunction with, say, USB Mass Storage. |
|
Enable Segger J-Link RTT libraries for platforms that support it. Selection of this option enables use of RTT for various subsystems. Note that by enabling this option, RTT buffers consume more RAM. |
|
Enable driver for VCNL4040 sensors. |
|
Enable Ambient Light Sense (ALS). |
|
Priority of thread used by the driver to handle interrupts. |
|
Stack size of thread used by the driver to handle interrupts. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
IRQ implementation for LiteX VexRiscv |
|
Enable support for the VIDEO. |
|
Alignment of the video pool’s buffer |
|
Number of maximum sized buffer in the video pool |
|
Size of the largest buffer in the video pool |
|
System initialization priority for video drivers. |
|
NXP MCUX CMOS Sensor Interface (CSI) driver |
|
Enable driver for MT9M114 CMOS digital image sensor device. |
|
Enable driver for OV7725 CMOS digital image sensor device. |
|
Enable video pattern generator (for testing purposes). |
|
This contains various drivers meant to support and expose features when Zephyr is running as a guest in a virtualized or emulated environment. |
|
Enable driver for VL53L0X I2C-based time of flight sensor. |
|
Threshold used for proximity detection when sensor is used with SENSOR_CHAN_PROX. |
|
Include support for watchdogs. |
|
Enable CMSDK APB Watchdog (WDOG_CMSDK_APB) Driver for ARM family of MCUs. |
|
Enable this setting to allow WDOG to be automatically started during device initialization. Note that once WDOG is started it must be reloaded before the counter reaches 0, otherwise the MCU will be reset. |
|
Set the IRQ line used by the WDT device. Very few lines can be chosen here, as it must be a level 4 interrupt. |
|
Set the IRQ line used by the WDT device. Very few lines can be chosen here, as it must be a level 4 interrupt. |
|
Disable watchdog at Zephyr system startup. |
|
Enable WDT driver for ESP32. |
|
Enable WDOG driver for Silicon Labs Gecko MCUs. |
|
Enable the mcux imx wdog driver. |
|
Enable the mcux wdog driver. |
|
Enable the mcux wdog32 driver. |
|
Enable the mcux wwdt driver. |
|
Enable multistage operation of watchdog timeouts. |
|
Enable support for NPCX Watchdog driver. Besides watchdog functionality, it also provides the protection mechanism over software execution. After setting the configuration registers, the software can lock it to provide a higher level of protection against subsequent erroneous software action. Once a section of the TWD is locked, only reset or the unlock sequence releases it. |
|
This option defines the window in which a watchdog event must be handled, in units of 31ms. After this time window, the watchdog reset triggers immediately. |
|
Enable support for nrfx WDT driver for nRF MCU series. |
|
Enable WDT driver for Atmel SAM MCUs. |
|
Enable WDT driver for Atmel SAM0 MCUs. |
|
This option enables WDT driver for SiFive Freedom. |
|
Enable WDT driver for Microchip XEC MCU series. |
|
Wi-Fi Drivers |
|
Espressif ESP8266 and ESP32 support |
|
Use AT command set version 1.7. |
|
Use AT command set version 2.0. |
|
Fetch DNS servers from ESP chip with AT+CIPDNS? command and apply that list to system DNS resolver. |
|
ESP Station mode IP Address |
|
Use DHCP to get an IP Address. |
|
Gateway Address |
|
Network Mask |
|
Setup Static IP Address. |
|
Ring buffer size used by modem UART interface handler. |
|
Number of preallocated RX buffers used by modem command handler. |
|
Size of preallocated RX buffers used by modem command handler. |
|
Driver name |
|
This lets the ESP handle the TCP window so that data can flow at a rate that the driver can handle. Without this, data might get lost if the driver cannot empty the device buffer quickly enough. |
|
How long to wait for device to become ready after AT+RST has been sent. This can vary with chipset (ESP8266/ESP32) and firmware version. This is ignored if a reset pin is configured. |
|
Network interface RX net_pkt allocation timeout in milliseconds. |
|
This stack is used by the Espressif ESP RX thread. |
|
Priority of thread used for processing RX data. |
|
This stack is used by the work queue to pass off net_pkt data to the rest of the network stack, letting the rx thread continue processing data. |
|
Priority of thread used for processing driver work queue items. |
|
Inventek eS-WiFi support |
|
SPI Bus interface |
|
UART Bus interface |
|
Enable esWiFi shell |
|
This option sets the priority of the esWiFi threads. Do not touch it unless you know what you are doing. |
|
Wi-Fi device driver initialization priority. Do not mess with it unless you know what you are doing. Note that the priority needs to be lower than the net stack so that it can start before the networking sub-system. |
|
Enable support for Full-MAC Wi-Fi devices. |
|
SimpleLink Wi-Fi driver support |
|
SimpleLink uses the “FastConnect” feature to reconnect to the previously connected AP on startup. Should the Wi-Fi connection timeout, the SimpleLink driver will fail to initialize, and LOG an error. |
|
Set the maximum size of a network packet going through the chip. This sets the size of each buffer, in each buffer pool. Do not modify it unless you know what you are doing. |
|
The number of times, separated by a one second interval, to retry a request for the network list. |
|
Driver name |
|
The number of results to request on a Wi-Fi scan operation. Actual number returned may be less. Maximum is 30. |
|
WINC1500 driver support |
|
Set the number of buffer the driver will have access to in each of its buffer pools. |
|
Set the maximum size of a network packet going through the chip. This sets the size of each buffer, in each buffer pools. Do not modify it unless you know what you are doing. |
|
Driver name |
|
Set the number of sockets that can be managed through the driver and the chip. |
|
Region Asia |
|
Region Europe |
|
Region North America |
|
This option sets the priority of the thread handling WINC1500 HAL callbacks. Do not touch it unless you know what you are doing. |
|
This option sets the size of the stack used by the thread handling WINC1500 HAL callbacks. Do not touch it unless you know what you are doing. |
|
Enable LED strip driver for daisy chains of WS2812-ish (or WS2812B, WS2813, SK6812, or compatible) devices. |
|
The GPIO driver does bit-banging with inline assembly, and is not available on all SoCs. |
|
The SPI driver is portable, but requires significantly more memory (1 byte of overhead per bit of pixel data). |
|
Enable WWDG driver for STM32 line of MCUs |
|
If your local APIC supports x2APIC mode, turn this on. |
|
This module implements a kernel device driver for the Xilinx ZynqMP platform provides the standard “system clock driver” interfaces. If unchecked, no timer will be used. |
|
This is the index of TTC timer picked to provide system clock. |
|
Device driver initialization priority. |
|
Use simulator console to print messages. |
|
Enables a system timer driver for Xtensa based on the CCOUNT and CCOMPARE special registers. |
|
Index of the CCOMPARE register (and associated interrupt) used for the system timer. Xtensa CPUs have hard-configured interrupt priorities associated with each timer, and some of them can be unmaskable (and thus not usable by OS code that need synchronization, like the timer subsystem!). Choose carefully. Generally you want the timer with the highest priority maskable interrupt. |