amebadplus_clock.h File Reference

Realtek Amebadplus clock Devicetree bindings. More...

Go to the source code of this file.

Macros
AON domain clocks
#define	AMEBA_ATIM_CLK   1
	ATIM clock in AON domain.
#define	AMEBA_RTC_CLK   2
	RTC clock in AON domain.
SYSON domain clocks
#define	AMEBA_PWM0_CLK   3
	PWM0 clock in SYSON domain.
#define	AMEBA_PWM1_CLK   4
	PWM1 clock in SYSON domain.
#define	AMEBA_HTIM0_CLK   5
	HTIM0 clock in SYSON domain.
#define	AMEBA_HTIM1_CLK   6
	HTIM1 clock in SYSON domain.
#define	AMEBA_LEDC_CLK   7
	LEDC clock in SYSON domain.
#define	AMEBA_UART0_CLK   8
	UART0 clock in SYSON domain.
#define	AMEBA_UART1_CLK   9
	UART1 clock in SYSON domain.
#define	AMEBA_UART2_CLK   10
	UART2 clock in SYSON domain.
#define	AMEBA_LOGUART_CLK   11
	LOGUART clock in SYSON domain.
#define	AMEBA_DTIM_CLK   12
	DTIM clock in SYSON domain.
#define	AMEBA_ADC_CLK   13
	ADC clock in SYSON domain.
#define	AMEBA_GPIO_CLK   14
	GPIO clock in SYSON domain.
#define	AMEBA_LTIM0_CLK   15
	LTIM0 clock in SYSON domain.
#define	AMEBA_LTIM1_CLK   16
	LTIM1 clock in SYSON domain.
#define	AMEBA_LTIM2_CLK   17
	LTIM2 clock in SYSON domain.
#define	AMEBA_LTIM3_CLK   18
	LTIM3 clock in SYSON domain.
#define	AMEBA_LTIM4_CLK   19
	LTIM4 clock in SYSON domain.
#define	AMEBA_LTIM5_CLK   20
	LTIM5 clock in SYSON domain.
#define	AMEBA_LTIM6_CLK   21
	LTIM6 clock in SYSON domain.
#define	AMEBA_LTIM7_CLK   22
	LTIM7 clock in SYSON domain.
#define	AMEBA_PTIM0_CLK   23
	PTIM0 clock in SYSON domain.
#define	AMEBA_PTIM1_CLK   24
	PTIM1 clock in SYSON domain.
#define	AMEBA_KSCAN_CLK   25
	KSCAN clock in SYSON domain.
SoC domain clocks
#define	AMEBA_DMAC_CLK   26
	DMAC clock in SoC domain.
#define	AMEBA_SDIO_CLK   27
	SDIO clock in SoC domain.
#define	AMEBA_SPI0_CLK   28
	SPI0 clock in SoC domain.
#define	AMEBA_SPI1_CLK   29
	SPI1 clock in SoC domain.
#define	AMEBA_USB_CLK   30
	USB clock in SoC domain.
#define	AMEBA_FLASH_CLK   31
	Flash clock in SoC domain.
#define	AMEBA_PSRAM_CLK   32
	PSRAM clock in SoC domain.
#define	AMEBA_SPORT0_CLK   33
	SPORT0 clock in SoC domain.
#define	AMEBA_SPORT1_CLK   34
	SPORT1 clock in SoC domain.
#define	AMEBA_AC_CLK   35
	AC clock in SoC domain.
#define	AMEBA_IRDA_CLK   36
	IRDA clock in SoC domain.
#define	AMEBA_I2C0_CLK   37
	I2C0 clock in SoC domain.
#define	AMEBA_I2C1_CLK   38
	I2C1 clock in SoC domain.
#define	AMEBA_TRNG_CLK   39
	TRNG clock in SoC domain.
Misc clocks
#define	AMEBA_BTON_CLK   40
	BTON clock.
#define	AMEBA_AES_CLK   42
	AES clock (misc domain).
#define	AMEBA_CLK_MAX   43 /* clk idx max */
	Maximum clock index (one past the last valid index).
Peripheral clock helper macros
#define	AMEBA_NUMERICAL_PERIPH(name, n)
	Define a clock entry for a peripheral with numerical suffix.
#define	AMEBA_SINGLE_PERIPH(name)
	Define a clock entry for a single-instance peripheral.
#define	AMEBA_LTIM_PERIPHS
	LTIM clock peripheral mappings.
#define	AMEBA_PTIM_PERIPHS
	PTIM clock peripheral mappings.
#define	AMEBA_SPI_PERIPHS
	SPI clock peripheral mappings.
#define	AMEBA_SPORT_PERIPHS
	SPORT clock peripheral mappings.
#define	AMEBA_I2C_PERIPHS
	I2C clock peripheral mappings.
#define	AMEBA_PWM_PERIPHS
	PWM clock peripheral mappings.
#define	AMEBA_HTIM_PERIPHS
	HTIM clock peripheral mappings.
#define	AMEBA_UART_PERIPHS
	UART clock peripheral mappings.
#define	AMEBA_LOGUART_PERIPHS   AMEBA_SINGLE_PERIPH(LOGUART) /* AMEBA_LOGUART_CLK */
	LOGUART clock peripheral mapping.
#define	AMEBA_KSCAN_PERIPHS   AMEBA_SINGLE_PERIPH(KSCAN) /* AMEBA_KSCAN_CLK */
	KSCAN clock peripheral mapping.
#define	AMEBA_DMAC_PERIPHS   AMEBA_SINGLE_PERIPH(DMAC) /* AMEBA_DMAC_CLK */
	DMAC clock peripheral mapping.
#define	AMEBA_SDIO_PERIPHS   AMEBA_SINGLE_PERIPH(SDIO) /* AMEBA_SDIO_CLK */
	SDIO clock peripheral mapping.
#define	AMEBA_USB_PERIPHS   AMEBA_SINGLE_PERIPH(USB) /* AMEBA_USB_CLK */
	USB clock peripheral mapping.
#define	AMEBA_FLASH_PERIPHS   AMEBA_SINGLE_PERIPH(FLASH) /* AMEBA_FLASH_CLK */
	Flash clock peripheral mapping.
#define	AMEBA_PSRAM_PERIPHS   AMEBA_SINGLE_PERIPH(PSRAM) /* AMEBA_PSRAM_CLK */
	PSRAM clock peripheral mapping.
#define	AMEBA_AC_PERIPHS   AMEBA_SINGLE_PERIPH(AC) /* AMEBA_AC_CLK */
	AC clock peripheral mapping.
#define	AMEBA_IRDA_PERIPHS   AMEBA_SINGLE_PERIPH(IRDA) /* AMEBA_IRDA_CLK */
	IRDA clock peripheral mapping.
#define	AMEBA_TRNG_PERIPHS   AMEBA_SINGLE_PERIPH(TRNG) /* AMEBA_TRNG_CLK */
	TRNG clock peripheral mapping.
#define	AMEBA_RTC_PERIPHS   AMEBA_SINGLE_PERIPH(RTC) /* AMEBA_RTC_CLK */
	RTC clock peripheral mapping.
#define	AMEBA_LEDC_PERIPHS   AMEBA_SINGLE_PERIPH(LEDC) /* AMEBA_LEDC_CLK */
	LEDC clock peripheral mapping.
#define	AMEBA_ADC_PERIPHS   AMEBA_SINGLE_PERIPH(ADC) /* AMEBA_ADC_CLK */
	ADC clock peripheral mapping.
#define	AMEBA_GPIO_PERIPHS   AMEBA_SINGLE_PERIPH(GPIO) /* AMEBA_GPIO_CLK */
	GPIO clock peripheral mapping.
#define	AMEBA_BTON_PERIPHS   AMEBA_SINGLE_PERIPH(BTON) /* AMEBA_BTON_CLK */
	BTON clock peripheral mapping.
#define	AMEBA_CORE_PERIPHS
	Aggregated core peripheral clock mappings.

Detailed Description

Realtek Amebadplus clock Devicetree bindings.

Macro Definition Documentation

AMEBA_AC_CLK

#define AMEBA_AC_CLK   35

AC clock in SoC domain.

AMEBA_AC_PERIPHS

#define AMEBA_AC_PERIPHS   AMEBA_SINGLE_PERIPH(AC) /* AMEBA_AC_CLK */

AC clock peripheral mapping.

AMEBA_ADC_CLK

#define AMEBA_ADC_CLK   13

ADC clock in SYSON domain.

AMEBA_ADC_PERIPHS

#define AMEBA_ADC_PERIPHS   AMEBA_SINGLE_PERIPH(ADC) /* AMEBA_ADC_CLK */

ADC clock peripheral mapping.

AMEBA_AES_CLK

#define AMEBA_AES_CLK   42

AES clock (misc domain).

AMEBA_ATIM_CLK

#define AMEBA_ATIM_CLK   1

ATIM clock in AON domain.

AMEBA_BTON_CLK

#define AMEBA_BTON_CLK   40

BTON clock.

AMEBA_BTON_PERIPHS

#define AMEBA_BTON_PERIPHS   AMEBA_SINGLE_PERIPH(BTON) /* AMEBA_BTON_CLK */

BTON clock peripheral mapping.

AMEBA_CLK_MAX

#define AMEBA_CLK_MAX   43 /* clk idx max */

Maximum clock index (one past the last valid index).

AMEBA_CORE_PERIPHS

#define AMEBA_CORE_PERIPHS

Value:

        AMEBA_RTC_PERIPHS                                                                  \
        AMEBA_PWM_PERIPHS                                                                  \
        AMEBA_HTIM_PERIPHS                                                                 \
        AMEBA_LEDC_PERIPHS                                                                 \
        AMEBA_UART_PERIPHS                                                                 \
        AMEBA_LOGUART_PERIPHS                                                              \
        AMEBA_ADC_PERIPHS                                                                  \
        AMEBA_GPIO_PERIPHS                                                                 \
        AMEBA_LTIM_PERIPHS                                                                 \
        AMEBA_PTIM_PERIPHS                                                                 \
        AMEBA_KSCAN_PERIPHS                                                                \
        AMEBA_DMAC_PERIPHS                                                                 \
        AMEBA_SDIO_PERIPHS                                                                 \
        AMEBA_SPI_PERIPHS                                                                  \
        AMEBA_USB_PERIPHS                                                                  \
        AMEBA_FLASH_PERIPHS                                                                \
        AMEBA_SPORT_PERIPHS                                                                \
        AMEBA_AC_PERIPHS                                                                   \
        AMEBA_I2C_PERIPHS                                                                  \
        AMEBA_TRNG_PERIPHS                                                                 \
        AMEBA_BTON_PERIPHS

Aggregated core peripheral clock mappings.

This macro expands to mappings of all core peripherals used by the clock control implementation.

AMEBA_DMAC_CLK

#define AMEBA_DMAC_CLK   26

DMAC clock in SoC domain.

AMEBA_DMAC_PERIPHS

#define AMEBA_DMAC_PERIPHS   AMEBA_SINGLE_PERIPH(DMAC) /* AMEBA_DMAC_CLK */

DMAC clock peripheral mapping.

AMEBA_DTIM_CLK

#define AMEBA_DTIM_CLK   12

DTIM clock in SYSON domain.

AMEBA_FLASH_CLK

#define AMEBA_FLASH_CLK   31

Flash clock in SoC domain.

AMEBA_FLASH_PERIPHS

#define AMEBA_FLASH_PERIPHS   AMEBA_SINGLE_PERIPH(FLASH) /* AMEBA_FLASH_CLK */

Flash clock peripheral mapping.

AMEBA_GPIO_CLK

#define AMEBA_GPIO_CLK   14

GPIO clock in SYSON domain.

AMEBA_GPIO_PERIPHS

#define AMEBA_GPIO_PERIPHS   AMEBA_SINGLE_PERIPH(GPIO) /* AMEBA_GPIO_CLK */

GPIO clock peripheral mapping.

AMEBA_HTIM0_CLK

#define AMEBA_HTIM0_CLK   5

HTIM0 clock in SYSON domain.

AMEBA_HTIM1_CLK

#define AMEBA_HTIM1_CLK   6

HTIM1 clock in SYSON domain.

AMEBA_HTIM_PERIPHS

#define AMEBA_HTIM_PERIPHS

Value:

        AMEBA_NUMERICAL_PERIPH(HTIM, 0) /* AMEBA_HTIM0_CLK */                              \
        AMEBA_NUMERICAL_PERIPH(HTIM, 1) /* AMEBA_HTIM1_CLK */

HTIM clock peripheral mappings.

AMEBA_I2C0_CLK

#define AMEBA_I2C0_CLK   37

I2C0 clock in SoC domain.

AMEBA_I2C1_CLK

#define AMEBA_I2C1_CLK   38

I2C1 clock in SoC domain.

AMEBA_I2C_PERIPHS

#define AMEBA_I2C_PERIPHS

Value:

        AMEBA_NUMERICAL_PERIPH(I2C, 0) /* AMEBA_I2C0_CLK */                                \
        AMEBA_NUMERICAL_PERIPH(I2C, 1) /* AMEBA_I2C1_CLK */

I2C clock peripheral mappings.

AMEBA_IRDA_CLK

#define AMEBA_IRDA_CLK   36

IRDA clock in SoC domain.

AMEBA_IRDA_PERIPHS

#define AMEBA_IRDA_PERIPHS   AMEBA_SINGLE_PERIPH(IRDA) /* AMEBA_IRDA_CLK */

IRDA clock peripheral mapping.

AMEBA_KSCAN_CLK

#define AMEBA_KSCAN_CLK   25

KSCAN clock in SYSON domain.

AMEBA_KSCAN_PERIPHS

#define AMEBA_KSCAN_PERIPHS   AMEBA_SINGLE_PERIPH(KSCAN) /* AMEBA_KSCAN_CLK */

KSCAN clock peripheral mapping.

AMEBA_LEDC_CLK

#define AMEBA_LEDC_CLK   7

LEDC clock in SYSON domain.

AMEBA_LEDC_PERIPHS

#define AMEBA_LEDC_PERIPHS   AMEBA_SINGLE_PERIPH(LEDC) /* AMEBA_LEDC_CLK */

LEDC clock peripheral mapping.

AMEBA_LOGUART_CLK

#define AMEBA_LOGUART_CLK   11

LOGUART clock in SYSON domain.

AMEBA_LOGUART_PERIPHS

#define AMEBA_LOGUART_PERIPHS   AMEBA_SINGLE_PERIPH(LOGUART) /* AMEBA_LOGUART_CLK */

LOGUART clock peripheral mapping.

AMEBA_LTIM0_CLK

#define AMEBA_LTIM0_CLK   15

LTIM0 clock in SYSON domain.

AMEBA_LTIM1_CLK

#define AMEBA_LTIM1_CLK   16

LTIM1 clock in SYSON domain.

AMEBA_LTIM2_CLK

#define AMEBA_LTIM2_CLK   17

LTIM2 clock in SYSON domain.

AMEBA_LTIM3_CLK

#define AMEBA_LTIM3_CLK   18

LTIM3 clock in SYSON domain.

AMEBA_LTIM4_CLK

#define AMEBA_LTIM4_CLK   19

LTIM4 clock in SYSON domain.

AMEBA_LTIM5_CLK

#define AMEBA_LTIM5_CLK   20

LTIM5 clock in SYSON domain.

AMEBA_LTIM6_CLK

#define AMEBA_LTIM6_CLK   21

LTIM6 clock in SYSON domain.

AMEBA_LTIM7_CLK

#define AMEBA_LTIM7_CLK   22

LTIM7 clock in SYSON domain.

AMEBA_LTIM_PERIPHS

#define AMEBA_LTIM_PERIPHS

Value:

        AMEBA_NUMERICAL_PERIPH(LTIM, 0) /* AMEBA_LTIM0_CLK */                              \
        AMEBA_NUMERICAL_PERIPH(LTIM, 1) /* AMEBA_LTIM1_CLK */                              \
        AMEBA_NUMERICAL_PERIPH(LTIM, 2) /* AMEBA_LTIM2_CLK */                              \
        AMEBA_NUMERICAL_PERIPH(LTIM, 3) /* AMEBA_LTIM3_CLK */                              \
        AMEBA_NUMERICAL_PERIPH(LTIM, 4) /* AMEBA_LTIM4_CLK */                              \
        AMEBA_NUMERICAL_PERIPH(LTIM, 5) /* AMEBA_LTIM5_CLK */                              \
        AMEBA_NUMERICAL_PERIPH(LTIM, 6) /* AMEBA_LTIM6_CLK */                              \
        AMEBA_NUMERICAL_PERIPH(LTIM, 7) /* AMEBA_LTIM7_CLK */

LTIM clock peripheral mappings.

AMEBA_NUMERICAL_PERIPH

#define AMEBA_NUMERICAL_PERIPH	(		name,
			n )

Value:

        [AMEBA_##name##n##_CLK] = {                                                        \
                .parent = AMEBA_RCC_NO_PARENT,                                             \
                .cke = APBPeriph_##name##n##_CLOCK,                                        \
                .fen = APBPeriph_##name##n,                                                \
        },

Define a clock entry for a peripheral with numerical suffix.

Used for peripherals with an index, for example SPI0, SPI1, UART0.

Parameters

name	Peripheral base name
n	Peripheral index

AMEBA_PSRAM_CLK

#define AMEBA_PSRAM_CLK   32

PSRAM clock in SoC domain.

AMEBA_PSRAM_PERIPHS

#define AMEBA_PSRAM_PERIPHS   AMEBA_SINGLE_PERIPH(PSRAM) /* AMEBA_PSRAM_CLK */

PSRAM clock peripheral mapping.

AMEBA_PTIM0_CLK

#define AMEBA_PTIM0_CLK   23

PTIM0 clock in SYSON domain.

AMEBA_PTIM1_CLK

#define AMEBA_PTIM1_CLK   24

PTIM1 clock in SYSON domain.

AMEBA_PTIM_PERIPHS

#define AMEBA_PTIM_PERIPHS

Value:

        AMEBA_NUMERICAL_PERIPH(PTIM, 0) /* AMEBA_PTIM0_CLK */                              \
        AMEBA_NUMERICAL_PERIPH(PTIM, 1) /* AMEBA_PTIM1_CLK */

PTIM clock peripheral mappings.

AMEBA_PWM0_CLK

#define AMEBA_PWM0_CLK   3

PWM0 clock in SYSON domain.

AMEBA_PWM1_CLK

#define AMEBA_PWM1_CLK   4

PWM1 clock in SYSON domain.

AMEBA_PWM_PERIPHS

#define AMEBA_PWM_PERIPHS

Value:

        AMEBA_NUMERICAL_PERIPH(PWM, 0) /* AMEBA_PWM0_CLK */                                \
        AMEBA_NUMERICAL_PERIPH(PWM, 1) /* AMEBA_PWM1_CLK */

PWM clock peripheral mappings.

AMEBA_RTC_CLK

#define AMEBA_RTC_CLK   2

RTC clock in AON domain.

AMEBA_RTC_PERIPHS

#define AMEBA_RTC_PERIPHS   AMEBA_SINGLE_PERIPH(RTC) /* AMEBA_RTC_CLK */

RTC clock peripheral mapping.

AMEBA_SDIO_CLK

#define AMEBA_SDIO_CLK   27

SDIO clock in SoC domain.

AMEBA_SDIO_PERIPHS

#define AMEBA_SDIO_PERIPHS   AMEBA_SINGLE_PERIPH(SDIO) /* AMEBA_SDIO_CLK */

SDIO clock peripheral mapping.

AMEBA_SINGLE_PERIPH

#define AMEBA_SINGLE_PERIPH

(

name

)

Value:

        [AMEBA_##name##_CLK] = {                                                           \
                .parent = AMEBA_RCC_NO_PARENT,                                             \
                .cke = APBPeriph_##name##_CLOCK,                                           \
                .fen = APBPeriph_##name,                                                   \
        },

Define a clock entry for a single-instance peripheral.

Used for peripherals that have only one instance, for example DMAC, SDIO, USB, TRNG, etc.

Parameters

name	Peripheral name

AMEBA_SPI0_CLK

#define AMEBA_SPI0_CLK   28

SPI0 clock in SoC domain.

AMEBA_SPI1_CLK

#define AMEBA_SPI1_CLK   29

SPI1 clock in SoC domain.

AMEBA_SPI_PERIPHS

#define AMEBA_SPI_PERIPHS

Value:

        AMEBA_NUMERICAL_PERIPH(SPI, 0) /* AMEBA_SPI0_CLK */                                \
        AMEBA_NUMERICAL_PERIPH(SPI, 1) /* AMEBA_SPI1_CLK */

SPI clock peripheral mappings.

AMEBA_SPORT0_CLK

#define AMEBA_SPORT0_CLK   33

SPORT0 clock in SoC domain.

AMEBA_SPORT1_CLK

#define AMEBA_SPORT1_CLK   34

SPORT1 clock in SoC domain.

AMEBA_SPORT_PERIPHS

#define AMEBA_SPORT_PERIPHS

Value:

        AMEBA_NUMERICAL_PERIPH(SPORT, 0) /* AMEBA_SPORT0_CLK */                            \
        AMEBA_NUMERICAL_PERIPH(SPORT, 1) /* AMEBA_SPORT1_CLK */

SPORT clock peripheral mappings.

AMEBA_TRNG_CLK

#define AMEBA_TRNG_CLK   39

TRNG clock in SoC domain.

AMEBA_TRNG_PERIPHS

#define AMEBA_TRNG_PERIPHS   AMEBA_SINGLE_PERIPH(TRNG) /* AMEBA_TRNG_CLK */

TRNG clock peripheral mapping.

AMEBA_UART0_CLK

#define AMEBA_UART0_CLK   8

UART0 clock in SYSON domain.

AMEBA_UART1_CLK

#define AMEBA_UART1_CLK   9

UART1 clock in SYSON domain.

AMEBA_UART2_CLK

#define AMEBA_UART2_CLK   10

UART2 clock in SYSON domain.

AMEBA_UART_PERIPHS

#define AMEBA_UART_PERIPHS

Value:

        AMEBA_NUMERICAL_PERIPH(UART, 0) /* AMEBA_UART0_CLK */                              \
        AMEBA_NUMERICAL_PERIPH(UART, 1) /* AMEBA_UART1_CLK */                              \
        AMEBA_NUMERICAL_PERIPH(UART, 2) /* AMEBA_UART2_CLK */

UART clock peripheral mappings.

AMEBA_USB_CLK

#define AMEBA_USB_CLK   30

USB clock in SoC domain.

AMEBA_USB_PERIPHS

#define AMEBA_USB_PERIPHS   AMEBA_SINGLE_PERIPH(USB) /* AMEBA_USB_CLK */

USB clock peripheral mapping.