stm32g0_clock.h File Reference

#include "stm32_common_clocks.h"

Go to the source code of this file.

Macros
#define	STM32_CLOCK_BUS_IOP   0x034
	Bus clocks.
#define	STM32_CLOCK_BUS_AHB1   0x038
#define	STM32_CLOCK_BUS_APB1   0x03c
#define	STM32_CLOCK_BUS_APB1_2   0x040
#define	STM32_PERIPH_BUS_MIN   STM32_CLOCK_BUS_IOP
#define	STM32_PERIPH_BUS_MAX   STM32_CLOCK_BUS_APB1_2
#define	STM32_SRC_HSI   (STM32_SRC_LSI + 1)
	Domain clocks.
#define	STM32_SRC_HSI48   (STM32_SRC_HSI + 1)
#define	STM32_SRC_MSI   (STM32_SRC_HSI48 + 1)
#define	STM32_SRC_HSE   (STM32_SRC_MSI + 1)
#define	STM32_SRC_PCLK   (STM32_SRC_HSE + 1)
	Peripheral bus clock.
#define	STM32_SRC_PLL_P   (STM32_SRC_PCLK + 1)
	PLL clock outputs.
#define	STM32_SRC_PLL_Q   (STM32_SRC_PLL_P + 1)
#define	STM32_SRC_PLL_R   (STM32_SRC_PLL_Q + 1)
#define	CFGR_REG   0x08
	RCC_CFGR register offset.
#define	CCIPR_REG   0x54
	RCC_CCIPR register offset.
#define	CCIPR2_REG   0x58
#define	BDCR_REG   0x5C
	RCC_BDCR register offset.
#define	MCO1_SEL(val)
	Device domain clocks selection helpers.
#define	MCO1_PRE(val)
#define	MCO2_SEL(val)
#define	MCO2_PRE(val)
#define	USART1_SEL(val)
	CCIPR devices.
#define	USART2_SEL(val)
#define	USART3_SEL(val)
#define	CEC_SEL(val)
#define	LPUART2_SEL(val)
#define	LPUART1_SEL(val)
#define	I2C1_SEL(val)
#define	I2C2_I2S1_SEL(val)
#define	LPTIM1_SEL(val)
#define	LPTIM2_SEL(val)
#define	TIM1_SEL(val)
#define	TIM15_SEL(val)
#define	RNG_SEL(val)
#define	ADC_SEL(val)
#define	I2S1_SEL(val)
	CCIPR2 devices.
#define	I2S2_SEL(val)
#define	FDCAN_SEL(val)
#define	USB_SEL(val)
#define	RTC_SEL(val)
	BDCR devices.
#define	MCO_PRE_DIV_1   0
#define	MCO_PRE_DIV_2   1
#define	MCO_PRE_DIV_4   2
#define	MCO_PRE_DIV_8   3
#define	MCO_PRE_DIV_16   4
#define	MCO_PRE_DIV_32   5
#define	MCO_PRE_DIV_64   6
#define	MCO_PRE_DIV_128   7
#define	MCO_SEL_SYSCLK   1
#define	MCO_SEL_HSI16   3
#define	MCO_SEL_HSE   4
#define	MCO_SEL_PLLRCLK   5
#define	MCO_SEL_LSI   6
#define	MCO_SEL_LSE   7

Macro Definition Documentation

ADC_SEL

#define ADC_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 3, 30, CCIPR_REG)

BDCR_REG

#define BDCR_REG   0x5C

RCC_BDCR register offset.

CCIPR2_REG

#define CCIPR2_REG   0x58

CCIPR_REG

#define CCIPR_REG   0x54

RCC_CCIPR register offset.

CEC_SEL

#define CEC_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 1, 6, CCIPR_REG)

CFGR_REG

#define CFGR_REG   0x08

RCC_CFGR register offset.

FDCAN_SEL

#define FDCAN_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR2_REG)

I2C1_SEL

#define I2C1_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR_REG)

I2C2_I2S1_SEL

#define I2C2_I2S1_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 3, 14, CCIPR_REG)

I2S1_SEL

#define I2S1_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR2_REG)

CCIPR2 devices.

I2S2_SEL

#define I2S2_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR2_REG)

LPTIM1_SEL

#define LPTIM1_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR_REG)

LPTIM2_SEL

#define LPTIM2_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR_REG)

LPUART1_SEL

#define LPUART1_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR_REG)

LPUART2_SEL

#define LPUART2_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR_REG)

MCO1_PRE

#define MCO1_PRE

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 15, 28, CFGR_REG)

MCO1_SEL

#define MCO1_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 15, 24, CFGR_REG)

Device domain clocks selection helpers.

CFGR devices

MCO2_PRE

#define MCO2_PRE

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 15, 20, CFGR_REG)

MCO2_SEL

#define MCO2_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 15, 16, CFGR_REG)

MCO_PRE_DIV_1

#define MCO_PRE_DIV_1   0

MCO_PRE_DIV_128

#define MCO_PRE_DIV_128   7

MCO_PRE_DIV_16

#define MCO_PRE_DIV_16   4

MCO_PRE_DIV_2

#define MCO_PRE_DIV_2   1

MCO_PRE_DIV_32

#define MCO_PRE_DIV_32   5

MCO_PRE_DIV_4

#define MCO_PRE_DIV_4   2

MCO_PRE_DIV_64

#define MCO_PRE_DIV_64   6

MCO_PRE_DIV_8

#define MCO_PRE_DIV_8   3

MCO_SEL_HSE

#define MCO_SEL_HSE   4

MCO_SEL_HSI16

#define MCO_SEL_HSI16   3

MCO_SEL_LSE

#define MCO_SEL_LSE   7

MCO_SEL_LSI

#define MCO_SEL_LSI   6

MCO_SEL_PLLRCLK

#define MCO_SEL_PLLRCLK   5

MCO_SEL_SYSCLK

#define MCO_SEL_SYSCLK   1

RNG_SEL

#define RNG_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 3, 26, CCIPR_REG)

RTC_SEL

#define RTC_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG)

BDCR devices.

STM32_CLOCK_BUS_AHB1

#define STM32_CLOCK_BUS_AHB1   0x038

STM32_CLOCK_BUS_APB1

#define STM32_CLOCK_BUS_APB1   0x03c

STM32_CLOCK_BUS_APB1_2

#define STM32_CLOCK_BUS_APB1_2   0x040

STM32_CLOCK_BUS_IOP

#define STM32_CLOCK_BUS_IOP   0x034

Bus clocks.

STM32_PERIPH_BUS_MAX

#define STM32_PERIPH_BUS_MAX   STM32_CLOCK_BUS_APB1_2

STM32_PERIPH_BUS_MIN

#define STM32_PERIPH_BUS_MIN   STM32_CLOCK_BUS_IOP

STM32_SRC_HSE

#define STM32_SRC_HSE   (STM32_SRC_MSI + 1)

STM32_SRC_HSI

#define STM32_SRC_HSI   (STM32_SRC_LSI + 1)

Domain clocks.

System clock Fixed clocks

STM32_SRC_HSI48

#define STM32_SRC_HSI48   (STM32_SRC_HSI + 1)

STM32_SRC_MSI

#define STM32_SRC_MSI   (STM32_SRC_HSI48 + 1)

STM32_SRC_PCLK

#define STM32_SRC_PCLK   (STM32_SRC_HSE + 1)

Peripheral bus clock.

STM32_SRC_PLL_P

#define STM32_SRC_PLL_P   (STM32_SRC_PCLK + 1)

PLL clock outputs.

STM32_SRC_PLL_Q

#define STM32_SRC_PLL_Q   (STM32_SRC_PLL_P + 1)

STM32_SRC_PLL_R

#define STM32_SRC_PLL_R   (STM32_SRC_PLL_Q + 1)

TIM15_SEL

#define TIM15_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 1, 24, CCIPR_REG)

TIM1_SEL

#define TIM1_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 1, 22, CCIPR_REG)

USART1_SEL

#define USART1_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR_REG)

CCIPR devices.

USART2_SEL

#define USART2_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR_REG)

USART3_SEL

#define USART3_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR_REG)

USB_SEL

#define USB_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR2_REG)