stm32g4_clock.h File Reference

#include "stm32_common_clocks.h"

Go to the source code of this file.

Macros
#define	STM32_CLOCK_BUS_AHB1   0x048
	Bus clocks.
#define	STM32_CLOCK_BUS_AHB2   0x04c
#define	STM32_CLOCK_BUS_AHB3   0x050
#define	STM32_CLOCK_BUS_APB1   0x058
#define	STM32_CLOCK_BUS_APB1_2   0x05c
#define	STM32_CLOCK_BUS_APB2   0x060
#define	STM32_PERIPH_BUS_MIN   STM32_CLOCK_BUS_AHB1
#define	STM32_PERIPH_BUS_MAX   STM32_CLOCK_BUS_APB2
#define	STM32_SRC_HSI   (STM32_SRC_LSI + 1)
	Domain clocks.
#define	STM32_SRC_HSI48   (STM32_SRC_HSI + 1)
#define	STM32_SRC_HSE   (STM32_SRC_HSI48 + 1)
#define	STM32_SRC_MSI   (STM32_SRC_HSE + 1)
#define	STM32_SRC_PCLK   (STM32_SRC_MSI + 1)
	Bus clock.
#define	STM32_SRC_TIMPCLK1   (STM32_SRC_PCLK + 1)
#define	STM32_SRC_TIMPCLK2   (STM32_SRC_TIMPCLK1 + 1)
#define	STM32_SRC_PLL_P   (STM32_SRC_TIMPCLK2 + 1)
	PLL clock outputs.
#define	STM32_SRC_PLL_Q   (STM32_SRC_PLL_P + 1)
#define	STM32_SRC_PLL_R   (STM32_SRC_PLL_Q + 1)
#define	CCIPR_REG   0x88
	RCC_CCIPR register offset.
#define	CCIPR2_REG   0x9C
#define	BDCR_REG   0x90
	RCC_BDCR register offset.
#define	USART1_SEL(val)
	Device domain clocks selection helpers.
#define	USART2_SEL(val)
#define	USART3_SEL(val)
#define	USART4_SEL(val)
#define	USART5_SEL(val)
#define	LPUART1_SEL(val)
#define	I2C1_SEL(val)
#define	I2C2_SEL(val)
#define	I2C3_SEL(val)
#define	LPTIM1_SEL(val)
#define	SAI1_SEL(val)
#define	I2S23_SEL(val)
#define	FDCAN_SEL(val)
#define	CLK48_SEL(val)
#define	ADC12_SEL(val)
#define	ADC34_SEL(val)
#define	I2C4_SEL(val)
	CCIPR2 devices.
#define	QSPI_SEL(val)
#define	RTC_SEL(val)
	BDCR devices.

Macro Definition Documentation

ADC12_SEL

#define ADC12_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 29, 28, CCIPR_REG)

ADC34_SEL

#define ADC34_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 31, 30, CCIPR_REG)

BDCR_REG

#define BDCR_REG   0x90

RCC_BDCR register offset.

CCIPR2_REG

#define CCIPR2_REG   0x9C

CCIPR_REG

#define CCIPR_REG   0x88

RCC_CCIPR register offset.

CLK48_SEL

#define CLK48_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 27, 26, CCIPR_REG)

FDCAN_SEL

#define FDCAN_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 25, 24, CCIPR_REG)

I2C1_SEL

#define I2C1_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 13, 12, CCIPR_REG)

I2C2_SEL

#define I2C2_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 15, 14, CCIPR_REG)

I2C3_SEL

#define I2C3_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 17, 16, CCIPR_REG)

I2C4_SEL

#define I2C4_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 1, 0, CCIPR2_REG)

CCIPR2 devices.

I2S23_SEL

#define I2S23_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 23, 22, CCIPR_REG)

LPTIM1_SEL

#define LPTIM1_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 19, 18, CCIPR_REG)

LPUART1_SEL

#define LPUART1_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 11, 10, CCIPR_REG)

QSPI_SEL

#define QSPI_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 21, 20, CCIPR2_REG)

RTC_SEL

#define RTC_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 9, 8, BDCR_REG)

BDCR devices.

SAI1_SEL

#define SAI1_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 21, 20, CCIPR_REG)

STM32_CLOCK_BUS_AHB1

#define STM32_CLOCK_BUS_AHB1   0x048

Bus clocks.

STM32_CLOCK_BUS_AHB2

#define STM32_CLOCK_BUS_AHB2   0x04c

STM32_CLOCK_BUS_AHB3

#define STM32_CLOCK_BUS_AHB3   0x050

STM32_CLOCK_BUS_APB1

#define STM32_CLOCK_BUS_APB1   0x058

STM32_CLOCK_BUS_APB1_2

#define STM32_CLOCK_BUS_APB1_2   0x05c

STM32_CLOCK_BUS_APB2

#define STM32_CLOCK_BUS_APB2   0x060

STM32_PERIPH_BUS_MAX

#define STM32_PERIPH_BUS_MAX   STM32_CLOCK_BUS_APB2

STM32_PERIPH_BUS_MIN

#define STM32_PERIPH_BUS_MIN   STM32_CLOCK_BUS_AHB1

STM32_SRC_HSE

#define STM32_SRC_HSE   (STM32_SRC_HSI48 + 1)

STM32_SRC_HSI

#define STM32_SRC_HSI   (STM32_SRC_LSI + 1)

Domain clocks.

System clock Fixed clocks

STM32_SRC_HSI48

#define STM32_SRC_HSI48   (STM32_SRC_HSI + 1)

STM32_SRC_MSI

#define STM32_SRC_MSI   (STM32_SRC_HSE + 1)

STM32_SRC_PCLK

#define STM32_SRC_PCLK   (STM32_SRC_MSI + 1)

Bus clock.

STM32_SRC_PLL_P

#define STM32_SRC_PLL_P   (STM32_SRC_TIMPCLK2 + 1)

PLL clock outputs.

STM32_SRC_PLL_Q

#define STM32_SRC_PLL_Q   (STM32_SRC_PLL_P + 1)

STM32_SRC_PLL_R

#define STM32_SRC_PLL_R   (STM32_SRC_PLL_Q + 1)

STM32_SRC_TIMPCLK1

#define STM32_SRC_TIMPCLK1   (STM32_SRC_PCLK + 1)

STM32_SRC_TIMPCLK2

#define STM32_SRC_TIMPCLK2   (STM32_SRC_TIMPCLK1 + 1)

USART1_SEL

#define USART1_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 1, 0, CCIPR_REG)

Device domain clocks selection helpers.

CCIPR devices

USART2_SEL

#define USART2_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR_REG)

USART3_SEL

#define USART3_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 5, 4, CCIPR_REG)

USART4_SEL

#define USART4_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 7, 6, CCIPR_REG)

USART5_SEL

#define USART5_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 9, 8, CCIPR_REG)