Go to the source code of this file.
◆ CCIPR_REG
RCC_CCIPR register offset.
◆ CSR_REG
◆ HSI48_SEL
Value:
#define STM32_DT_CLOCK_SELECT(val, mask, shift, reg)
Pack STM32 source clock selection RCC register bit fields for the DT.
Definition stm32_common_clocks.h:46
#define CCIPR_REG
RCC_CCIPR register offset.
Definition stm32l0_clock.h:35
◆ I2C1_SEL
◆ I2C3_SEL
◆ LPTIM1_SEL
#define LPTIM1_SEL |
( |
| val | ) |
|
◆ LPUART1_SEL
#define LPUART1_SEL |
( |
| val | ) |
|
◆ RTC_SEL
Value:
#define CSR_REG
RCC_CSR register offset.
Definition stm32l0_clock.h:38
CSR devices.
◆ STM32_CLOCK_BUS_AHB1
#define STM32_CLOCK_BUS_AHB1 0x030 |
◆ STM32_CLOCK_BUS_APB1
#define STM32_CLOCK_BUS_APB1 0x038 |
◆ STM32_CLOCK_BUS_APB2
#define STM32_CLOCK_BUS_APB2 0x034 |
◆ STM32_CLOCK_BUS_IOP
#define STM32_CLOCK_BUS_IOP 0x02c |
◆ STM32_PERIPH_BUS_MAX
◆ STM32_PERIPH_BUS_MIN
◆ STM32_SRC_HSE
Domain clocks.
System clock Fixed clocks
◆ STM32_SRC_HSI
◆ STM32_SRC_HSI48
◆ STM32_SRC_PCLK
◆ USART1_SEL
#define USART1_SEL |
( |
| val | ) |
|
Value:
Device domain clocks selection helpers.
CCIPR devices
◆ USART2_SEL
#define USART2_SEL |
( |
| val | ) |
|