clock_mchp_subsys_dfll48m_config Struct Reference

DFLL 48MHz configuration structure. More...

#include <zephyr/drivers/clock_control/mchp_clock_pic32cz_ca.h>

Data Fields
bool	on_demand_en
	configure oscillator to ON, when a peripheral is requesting it as a source
bool	closed_loop_en
	Enable closed-loop operation.
enum clock_mchp_gclkgen	src
	Reference source clock selection.
uint16_t	multiply_factor
	Determines the ratio of the CLK_DFLL48M output frequency to the CLK_DFLL48M_REF input frequency (0 - 65535).

Detailed Description

DFLL 48MHz configuration structure.

Field Documentation

closed_loop_en

bool clock_mchp_subsys_dfll48m_config::closed_loop_en

Enable closed-loop operation.

multiply_factor

uint16_t clock_mchp_subsys_dfll48m_config::multiply_factor

Determines the ratio of the CLK_DFLL48M output frequency to the CLK_DFLL48M_REF input frequency (0 - 65535).

on_demand_en

bool clock_mchp_subsys_dfll48m_config::on_demand_en

configure oscillator to ON, when a peripheral is requesting it as a source

src

enum clock_mchp_gclkgen clock_mchp_subsys_dfll48m_config::src

Reference source clock selection.

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The documentation for this struct was generated from the following file:

• zephyr/drivers/clock_control/mchp_clock_pic32cz_ca.h