mchp_clock_pic32cz_ca.h

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/*
 * Copyright (c) 2025-2026 Microchip Technology Inc.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

 
#ifndef INCLUDE_ZEPHYR_DRIVERS_CLOCK_CONTROL_MCHP_CLOCK_PIC32CZ_CA_H_
#define INCLUDE_ZEPHYR_DRIVERS_CLOCK_CONTROL_MCHP_CLOCK_PIC32CZ_CA_H_
 
#include <zephyr/dt-bindings/clock/mchp_pic32cz_ca_clock.h>


struct clock_mchp_subsys_xosc_config {
        bool on_demand_en;
};

enum clock_mchp_gclkgen {
        CLOCK_MCHP_GCLKGEN_GEN0,  
        CLOCK_MCHP_GCLKGEN_GEN1,  
        CLOCK_MCHP_GCLKGEN_GEN2,  
        CLOCK_MCHP_GCLKGEN_GEN3,  
        CLOCK_MCHP_GCLKGEN_GEN4,  
        CLOCK_MCHP_GCLKGEN_GEN5,  
        CLOCK_MCHP_GCLKGEN_GEN6,  
        CLOCK_MCHP_GCLKGEN_GEN7,  
        CLOCK_MCHP_GCLKGEN_GEN8,  
        CLOCK_MCHP_GCLKGEN_GEN9,  
        CLOCK_MCHP_GCLKGEN_GEN10, 
        CLOCK_MCHP_GCLKGEN_GEN11, 
        CLOCK_MCHP_GCLKGEN_GEN12, 
        CLOCK_MCHP_GCLKGEN_GEN13, 
        CLOCK_MCHP_GCLKGEN_GEN14, 
        CLOCK_MCHP_GCLKGEN_GEN15  
};

struct clock_mchp_subsys_dfll48m_config {
        bool on_demand_en;

        bool closed_loop_en;

        enum clock_mchp_gclkgen src;

        uint16_t multiply_factor;
};

enum clock_mchp_dpll_src_clock {
        CLOCK_MCHP_DPLL_SRC_GCLK0,   
        CLOCK_MCHP_DPLL_SRC_GCLK1,   
        CLOCK_MCHP_DPLL_SRC_GCLK2,   
        CLOCK_MCHP_DPLL_SRC_GCLK3,   
        CLOCK_MCHP_DPLL_SRC_GCLK4,   
        CLOCK_MCHP_DPLL_SRC_GCLK5,   
        CLOCK_MCHP_DPLL_SRC_GCLK6,   
        CLOCK_MCHP_DPLL_SRC_GCLK7,   
        CLOCK_MCHP_DPLL_SRC_GCLK8,   
        CLOCK_MCHP_DPLL_SRC_GCLK9,   
        CLOCK_MCHP_DPLL_SRC_GCLK10,  
        CLOCK_MCHP_DPLL_SRC_GCLK11,  
        CLOCK_MCHP_DPLL_SRC_GCLK12,  
        CLOCK_MCHP_DPLL_SRC_GCLK13,  
        CLOCK_MCHP_DPLL_SRC_GCLK14,  
        CLOCK_MCHP_DPLL_SRC_GCLK15,  
        CLOCK_MCHP_DPLL_SRC_XOSC,    
        CLOCK_MCHP_DPLL_SRC_DFLL48M, 
 
        CLOCK_MCHP_DPLL_SRC_MAX =
                CLOCK_MCHP_DPLL_SRC_DFLL48M 
};

struct clock_mchp_subsys_dpll_config {
        uint16_t feedback_divider_factor;

        uint8_t ref_division_factor;

        bool on_demand_en;

        enum clock_mchp_dpll_src_clock src;
};

struct clock_mchp_subsys_dpll_out_config {
        uint8_t output_division_factor;
};

enum clock_mchp_rtc_src_clock {
        CLOCK_MCHP_RTC_SRC_ULP1K = OSC32KCTRL_CLKSELCTRL_RTCSEL_ULP1K_Val,

        CLOCK_MCHP_RTC_SRC_ULP32K = OSC32KCTRL_CLKSELCTRL_RTCSEL_ULP32K_Val,

        CLOCK_MCHP_RTC_SRC_XOSC1K = OSC32KCTRL_CLKSELCTRL_RTCSEL_XOSC1K_Val,

        CLOCK_MCHP_RTC_SRC_XOSC32K = OSC32KCTRL_CLKSELCTRL_RTCSEL_XOSC32K_Val
};

struct clock_mchp_subsys_rtc_config {
        enum clock_mchp_rtc_src_clock src;
};

struct clock_mchp_subsys_xosc32k_config {
        bool on_demand_en;
};

enum clock_mchp_gclk_src_clock {
        CLOCK_MCHP_GCLK_SRC_XOSC,              
        CLOCK_MCHP_GCLK_SRC_GCLKPIN,           
        CLOCK_MCHP_GCLK_SRC_GCLKGEN1,          
        CLOCK_MCHP_GCLK_SRC_OSCULP32K,         
        CLOCK_MCHP_GCLK_SRC_XOSC32K,           
        CLOCK_MCHP_GCLK_SRC_DFLL48M,           
        CLOCK_MCHP_GCLK_SRC_DPLL0_CLKOUT0,     
        CLOCK_MCHP_GCLK_SRC_DPLL0_CLKOUT1,     
        CLOCK_MCHP_GCLK_SRC_DPLL0_CLKOUT2,     
        CLOCK_MCHP_GCLK_SRC_DPLL0_CLKOUT3,     
        CLOCK_MCHP_GCLK_SRC_DPLL1_FRC_CLKOUT0, 
        CLOCK_MCHP_GCLK_SRC_DPLL1_FRC_CLKOUT1, 
        CLOCK_MCHP_GCLK_SRC_DPLL1_CLKOUT2,     
        CLOCK_MCHP_GCLK_SRC_DPLL1_CLKOUT3,     
 
        CLOCK_MCHP_GCLK_SRC_MAX =
                CLOCK_MCHP_GCLK_SRC_DPLL1_CLKOUT3 
};

struct clock_mchp_subsys_gclkgen_config {
        uint16_t div_factor;

        bool run_in_standby_en;

        enum clock_mchp_gclk_src_clock src;
};

struct clock_mchp_subsys_gclkperiph_config {
        enum clock_mchp_gclkgen src;
};

enum clock_mchp_mclk_cpu_div {
        CLOCK_MCHP_MCLK_CPU_DIV_1 = 1,    
        CLOCK_MCHP_MCLK_CPU_DIV_2 = 2,    
        CLOCK_MCHP_MCLK_CPU_DIV_4 = 4,    
        CLOCK_MCHP_MCLK_CPU_DIV_8 = 8,    
        CLOCK_MCHP_MCLK_CPU_DIV_16 = 16,  
        CLOCK_MCHP_MCLK_CPU_DIV_32 = 32,  
        CLOCK_MCHP_MCLK_CPU_DIV_64 = 64,  
        CLOCK_MCHP_MCLK_CPU_DIV_128 = 128 
};

struct clock_mchp_subsys_mclkcpu_config {
        enum clock_mchp_mclk_cpu_div division_factor;
};

typedef uint32_t *clock_mchp_rate_t;

 
#endif /* INCLUDE_ZEPHYR_DRIVERS_CLOCK_CONTROL_MCHP_CLOCK_PIC32CZ_CA_H_ */