mchp_clock_pic32cz_ca.h File Reference

Clock control header file for the Microchip PIC32CZ CA family. More...

#include <zephyr/dt-bindings/clock/mchp_pic32cz_ca_clock.h>

Go to the source code of this file.

Data Structures
struct	clock_mchp_subsys_xosc_config
	External oscillator (XOSC) configuration. More...
struct	clock_mchp_subsys_dfll48m_config
	DFLL 48MHz configuration structure. More...
struct	clock_mchp_subsys_dpll_config
	DPLL configuration structure. More...
struct	clock_mchp_subsys_dpll_out_config
	DPLL Output configuration structure. More...
struct	clock_mchp_subsys_rtc_config
	RTC clock configuration. More...
struct	clock_mchp_subsys_xosc32k_config
	32 kHz external oscillator (XOSC32K) configuration. More...
struct	clock_mchp_subsys_gclkgen_config
	GCLK generator configuration. More...
struct	clock_mchp_subsys_gclkperiph_config
	Peripheral GCLK channel configuration. More...
struct	clock_mchp_subsys_mclkcpu_config
	MCLK configuration structure. More...

Typedefs
typedef uint32_t *	clock_mchp_rate_t
	clock rate datatype

Enumerations
enum	clock_mchp_gclkgen {   CLOCK_MCHP_GCLKGEN_GEN0 , CLOCK_MCHP_GCLKGEN_GEN1 , CLOCK_MCHP_GCLKGEN_GEN2 , CLOCK_MCHP_GCLKGEN_GEN3 ,   CLOCK_MCHP_GCLKGEN_GEN4 , CLOCK_MCHP_GCLKGEN_GEN5 , CLOCK_MCHP_GCLKGEN_GEN6 , CLOCK_MCHP_GCLKGEN_GEN7 ,   CLOCK_MCHP_GCLKGEN_GEN8 , CLOCK_MCHP_GCLKGEN_GEN9 , CLOCK_MCHP_GCLKGEN_GEN10 , CLOCK_MCHP_GCLKGEN_GEN11 ,   CLOCK_MCHP_GCLKGEN_GEN12 , CLOCK_MCHP_GCLKGEN_GEN13 , CLOCK_MCHP_GCLKGEN_GEN14 , CLOCK_MCHP_GCLKGEN_GEN15 }
	Gclk generator numbers. More...
enum	clock_mchp_dpll_src_clock {   CLOCK_MCHP_DPLL_SRC_GCLK0 , CLOCK_MCHP_DPLL_SRC_GCLK1 , CLOCK_MCHP_DPLL_SRC_GCLK2 , CLOCK_MCHP_DPLL_SRC_GCLK3 ,   CLOCK_MCHP_DPLL_SRC_GCLK4 , CLOCK_MCHP_DPLL_SRC_GCLK5 , CLOCK_MCHP_DPLL_SRC_GCLK6 , CLOCK_MCHP_DPLL_SRC_GCLK7 ,   CLOCK_MCHP_DPLL_SRC_GCLK8 , CLOCK_MCHP_DPLL_SRC_GCLK9 , CLOCK_MCHP_DPLL_SRC_GCLK10 , CLOCK_MCHP_DPLL_SRC_GCLK11 ,   CLOCK_MCHP_DPLL_SRC_GCLK12 , CLOCK_MCHP_DPLL_SRC_GCLK13 , CLOCK_MCHP_DPLL_SRC_GCLK14 , CLOCK_MCHP_DPLL_SRC_GCLK15 ,   CLOCK_MCHP_DPLL_SRC_XOSC , CLOCK_MCHP_DPLL_SRC_DFLL48M , CLOCK_MCHP_DPLL_SRC_MAX }
	DPLL source clocks. More...
enum	clock_mchp_rtc_src_clock { CLOCK_MCHP_RTC_SRC_ULP1K = OSC32KCTRL_CLKSELCTRL_RTCSEL_ULP1K_Val , CLOCK_MCHP_RTC_SRC_ULP32K = OSC32KCTRL_CLKSELCTRL_RTCSEL_ULP32K_Val , CLOCK_MCHP_RTC_SRC_XOSC1K = OSC32KCTRL_CLKSELCTRL_RTCSEL_XOSC1K_Val , CLOCK_MCHP_RTC_SRC_XOSC32K = OSC32KCTRL_CLKSELCTRL_RTCSEL_XOSC32K_Val }
	RTC source clocks. More...
enum	clock_mchp_gclk_src_clock {   CLOCK_MCHP_GCLK_SRC_XOSC , CLOCK_MCHP_GCLK_SRC_GCLKPIN , CLOCK_MCHP_GCLK_SRC_GCLKGEN1 , CLOCK_MCHP_GCLK_SRC_OSCULP32K ,   CLOCK_MCHP_GCLK_SRC_XOSC32K , CLOCK_MCHP_GCLK_SRC_DFLL48M , CLOCK_MCHP_GCLK_SRC_DPLL0_CLKOUT0 , CLOCK_MCHP_GCLK_SRC_DPLL0_CLKOUT1 ,   CLOCK_MCHP_GCLK_SRC_DPLL0_CLKOUT2 , CLOCK_MCHP_GCLK_SRC_DPLL0_CLKOUT3 , CLOCK_MCHP_GCLK_SRC_DPLL1_FRC_CLKOUT0 , CLOCK_MCHP_GCLK_SRC_DPLL1_FRC_CLKOUT1 ,   CLOCK_MCHP_GCLK_SRC_DPLL1_CLKOUT2 , CLOCK_MCHP_GCLK_SRC_DPLL1_CLKOUT3 , CLOCK_MCHP_GCLK_SRC_MAX }
	Gclk Generator source clocks. More...
enum	clock_mchp_mclk_cpu_div {   CLOCK_MCHP_MCLK_CPU_DIV_1 = 1 , CLOCK_MCHP_MCLK_CPU_DIV_2 = 2 , CLOCK_MCHP_MCLK_CPU_DIV_4 = 4 , CLOCK_MCHP_MCLK_CPU_DIV_8 = 8 ,   CLOCK_MCHP_MCLK_CPU_DIV_16 = 16 , CLOCK_MCHP_MCLK_CPU_DIV_32 = 32 , CLOCK_MCHP_MCLK_CPU_DIV_64 = 64 , CLOCK_MCHP_MCLK_CPU_DIV_128 = 128 }
	division ratio of mclk prescaler for CPU More...

Detailed Description

Clock control header file for the Microchip PIC32CZ CA family.

This file provides clock driver interface definitions and structures for the PIC32CZ CA family.