clock_mchp_subsys_dpll_config Struct Reference

DPLL configuration structure. More...

#include <zephyr/drivers/clock_control/mchp_clock_pic32cz_ca.h>

Data Fields
uint16_t	feedback_divider_factor
	ratio of PLL's VCO output frequency to Reference input frequency
uint8_t	ref_division_factor
	Determines division factor of PLL input reference freq (1 ≤ REFDIV ≤ 63).
bool	on_demand_en
	configure oscillator to ON, when a peripheral is requesting it as a source
enum clock_mchp_dpll_src_clock	src
	Reference source clock selection.

Detailed Description

DPLL configuration structure.

Field Documentation

feedback_divider_factor

uint16_t clock_mchp_subsys_dpll_config::feedback_divider_factor

ratio of PLL's VCO output frequency to Reference input frequency

on_demand_en

bool clock_mchp_subsys_dpll_config::on_demand_en

configure oscillator to ON, when a peripheral is requesting it as a source

ref_division_factor

uint8_t clock_mchp_subsys_dpll_config::ref_division_factor

Determines division factor of PLL input reference freq (1 ≤ REFDIV ≤ 63).

src

enum clock_mchp_dpll_src_clock clock_mchp_subsys_dpll_config::src

Reference source clock selection.

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The documentation for this struct was generated from the following file:

• zephyr/drivers/clock_control/mchp_clock_pic32cz_ca.h