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/*

 * Copyright (c) 2024-2025 Renesas Electronics Corporation

 *

 * SPDX-License-Identifier: Apache-2.0

 */


#ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_RENESAS_RA_CGC_H_

#define ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_RENESAS_RA_CGC_H_


#include <zephyr/drivers/clock_control.h>

#include <zephyr/dt-bindings/clock/ra_clock.h>


#define RA_CGC_PROP_HAS_STATUS_OKAY_OR(node_id, prop, default_value)                               \

        COND_CODE_1(DT_NODE_HAS_STATUS(node_id, okay), \

                (DT_PROP(node_id, prop)), (default_value))


#define RA_CGC_CLK_SRC(node_id)                                                                    \

        COND_CODE_1(DT_NODE_HAS_STATUS(node_id, okay), \

                (UTIL_CAT(BSP_CLOCKS_SOURCE_, DT_NODE_FULL_NAME_UPPER_TOKEN(node_id))), \

                (BSP_CLOCKS_CLOCK_DISABLED))


#define RA_CGC_CLK_DIV(clk, prop, default_value)                                                   \

        UTIL_CAT(RA_CGC_DIV_, DT_NODE_FULL_NAME_UPPER_TOKEN(clk))                                  \

        (RA_CGC_PROP_HAS_STATUS_OKAY_OR(clk, prop, default_value))


#define RA_CGC_DIV_BCLK(n)       UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n)

#define RA_CGC_DIV_CANFDCLK(n)   UTIL_CAT(BSP_CLOCKS_CANFD_CLOCK_DIV_, n)

#define RA_CGC_DIV_CECCLK(n)     UTIL_CAT(BSP_CLOCKS_CEC_CLOCK_DIV_, n)

#define RA_CGC_DIV_CLKOUT(n)     UTIL_CAT(BSP_CLOCKS_CLKOUT_DIV_, n)

#define RA_CGC_DIV_CPUCLK0(n)    UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n)

#define RA_CGC_DIV_CPUCLK1(n)    UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n)

#define RA_CGC_DIV_MRPCLK(n)     UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n)

#define RA_CGC_DIV_CPUCLK(n)     UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n)

#define RA_CGC_DIV_FCLK(n)       UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n)

#define RA_CGC_DIV_I3CCLK(n)     UTIL_CAT(BSP_CLOCKS_I3C_CLOCK_DIV_, n)

#define RA_CGC_DIV_ICLK(n)       UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n)

#define RA_CGC_DIV_LCDCLK(n)     UTIL_CAT(BSP_CLOCKS_LCD_CLOCK_DIV_, n)

#define RA_CGC_DIV_OCTASPICLK(n) UTIL_CAT(BSP_CLOCKS_OCTA_CLOCK_DIV_, n)

#define RA_CGC_DIV_PCLKA(n)      UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n)

#define RA_CGC_DIV_PCLKB(n)      UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n)

#define RA_CGC_DIV_PCLKC(n)      UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n)

#define RA_CGC_DIV_PCLKD(n)      UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n)

#define RA_CGC_DIV_PCLKE(n)      UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n)

#define RA_CGC_DIV_PLL(n)        UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n)

#define RA_CGC_DIV_PLLP(n)       UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n)

#define RA_CGC_DIV_PLLQ(n)       UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n)

#define RA_CGC_DIV_PLLR(n)       UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n)

#define RA_CGC_DIV_PLL2(n)       UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n)

#define RA_CGC_DIV_PLL2P(n)      UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n)

#define RA_CGC_DIV_PLL2Q(n)      UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n)

#define RA_CGC_DIV_PLL2R(n)      UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n)

#define RA_CGC_DIV_SCICLK(n)     UTIL_CAT(BSP_CLOCKS_SCI_CLOCK_DIV_, n)

#define RA_CGC_DIV_SPICLK(n)     UTIL_CAT(BSP_CLOCKS_SPI_CLOCK_DIV_, n)

#define RA_CGC_DIV_U60CLK(n)     UTIL_CAT(BSP_CLOCKS_USB60_CLOCK_DIV_, n)

#define RA_CGC_DIV_UCLK(n)       UTIL_CAT(BSP_CLOCKS_USB_CLOCK_DIV_, n)

#define RA_CGC_DIV_SCISPICLK(n)  UTIL_CAT(BSP_CLOCKS_SCISPI_CLOCK_DIV_, n)

#define RA_CGC_DIV_GPTCLK(n)     UTIL_CAT(BSP_CLOCKS_GPT_CLOCK_DIV_, n)

#define RA_CGC_DIV_IICCLK(n)     UTIL_CAT(BSP_CLOCKS_IIC_CLOCK_DIV_, n)

#define RA_CGC_DIV_ADCCLK(n)     UTIL_CAT(BSP_CLOCKS_ADC_CLOCK_DIV_, n)

#define RA_CGC_DIV_MRICLK(n)     UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n)

#define RA_CGC_DIV_NPUCLK(n)     UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n)

#define RA_CGC_DIV_BCLKA(n)      UTIL_CAT(BSP_CLOCKS_BCLKA_CLOCK_DIV_, n)

#define RA_CGC_DIV_ESWCLK(n)     UTIL_CAT(BSP_CLOCKS_ESW_CLOCK_DIV_, n)


#define RA_CGC_DIV_ESWPHYCLK(n)                                                                    \

        UTIL_CAT(BSP_CLOCKS_ESWPHY_CLOCK_DIV_, n)


#define RA_CGC_DIV_ETHPHYCLK(n) UTIL_CAT(BSP_CLOCKS_ETHPHY_CLOCK_DIV_, n)

#define RA_CGC_DIV_ESCCLK(n)    UTIL_CAT(BSP_CLOCKS_ESC_CLOCK_DIV_, n)

#define RA_CGC_DIV_DSMIFCLK(n)  UTIL_CAT(BSP_CLOCKS_DSMIF_CLOCK_DIV_, n)


#define BSP_CLOCKS_SOURCE_PLL   BSP_CLOCKS_SOURCE_CLOCK_PLL

#define BSP_CLOCKS_SOURCE_PLLP  BSP_CLOCKS_SOURCE_CLOCK_PLL

#define BSP_CLOCKS_SOURCE_PLLQ  BSP_CLOCKS_SOURCE_CLOCK_PLL1Q

#define BSP_CLOCKS_SOURCE_PLLR  BSP_CLOCKS_SOURCE_CLOCK_PLL1R

#define BSP_CLOCKS_SOURCE_PLL2  BSP_CLOCKS_SOURCE_CLOCK_PLL2

#define BSP_CLOCKS_SOURCE_PLL2P BSP_CLOCKS_SOURCE_CLOCK_PLL2

#define BSP_CLOCKS_SOURCE_PLL2Q BSP_CLOCKS_SOURCE_CLOCK_PLL2Q

#define BSP_CLOCKS_SOURCE_PLL2R BSP_CLOCKS_SOURCE_CLOCK_PLL2R


#define BSP_CLOCKS_CLKOUT_DIV_1   (0)

#define BSP_CLOCKS_CLKOUT_DIV_2   (1)

#define BSP_CLOCKS_CLKOUT_DIV_4   (2)

#define BSP_CLOCKS_CLKOUT_DIV_8   (3)

#define BSP_CLOCKS_CLKOUT_DIV_16  (4)

#define BSP_CLOCKS_CLKOUT_DIV_32  (5)

#define BSP_CLOCKS_CLKOUT_DIV_64  (6)

#define BSP_CLOCKS_CLKOUT_DIV_128 (7)


struct clock_control_ra_pclk_cfg {

        uint32_t clk_src;

        uint32_t clk_div;

};


struct clock_control_ra_subsys_cfg {

        uint32_t mstp;

        uint32_t stop_bit;

};


#endif /* ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_RENESAS_RA_CGC_H_ */

clock_control.h
Main header file for clock control driver API.

ra_clock.h
Renesas RA Clock Generator Circuit (CGC) definitions for Zephyr.

uint32_t
__UINT32_TYPE__ uint32_t
Definition stdint.h:90

clock_control_ra_pclk_cfg
Peripheral clock configuration.
Definition renesas_ra_cgc.h:140

clock_control_ra_pclk_cfg::clk_div
uint32_t clk_div
Clock divider value.
Definition renesas_ra_cgc.h:142

clock_control_ra_pclk_cfg::clk_src
uint32_t clk_src
Clock source selection.
Definition renesas_ra_cgc.h:141

clock_control_ra_subsys_cfg
Subsystem clock control configuration.
Definition renesas_ra_cgc.h:148

clock_control_ra_subsys_cfg::mstp
uint32_t mstp
MSTP register index.
Definition renesas_ra_cgc.h:149

clock_control_ra_subsys_cfg::stop_bit
uint32_t stop_bit
Clock stop bit.
Definition renesas_ra_cgc.h:150