Zephyr API Documentation 4.1.99
A Scalable Open Source RTOS
 4.1.99
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renesas-rz-gpio.h File Reference

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Macros

#define RZ_GPIO_IOLH_SHIFT   8U
 RZ/A,G,V-specific GPIO Flags The pin driving ability flags are encoded in the 8 upper bits of gpio_dt_flags_t as follows:
 
#define RZ_GPIO_IOLH_SET(iolh_val)
 
#define RZ_GPIO_FILTER_SHIFT   10U
 
#define RZ_GPIO_FILNUM_SHIFT   1U
 
#define RZ_GPIO_FILCLKSEL_SHIFT   3U
 
#define RZ_GPIO_FILTER_SET(fillonoff, filnum, filclksel)
 

Macro Definition Documentation

◆ RZ_GPIO_FILCLKSEL_SHIFT

#define RZ_GPIO_FILCLKSEL_SHIFT   3U

◆ RZ_GPIO_FILNUM_SHIFT

#define RZ_GPIO_FILNUM_SHIFT   1U

◆ RZ_GPIO_FILTER_SET

#define RZ_GPIO_FILTER_SET ( fillonoff,
filnum,
filclksel )
Value:
(((fillonoff) | ((filnum) << RZ_GPIO_FILNUM_SHIFT) | \
((filclksel) << RZ_GPIO_FILCLKSEL_SHIFT)) \
#define RZ_GPIO_FILNUM_SHIFT
Definition renesas-rz-gpio.h:34
#define RZ_GPIO_FILTER_SHIFT
Definition renesas-rz-gpio.h:33
#define RZ_GPIO_FILCLKSEL_SHIFT
Definition renesas-rz-gpio.h:35

◆ RZ_GPIO_FILTER_SHIFT

#define RZ_GPIO_FILTER_SHIFT   10U

◆ RZ_GPIO_IOLH_SET

#define RZ_GPIO_IOLH_SET ( iolh_val)
Value:
(iolh_val << RZ_GPIO_IOLH_SHIFT)
#define RZ_GPIO_IOLH_SHIFT
RZ/A,G,V-specific GPIO Flags The pin driving ability flags are encoded in the 8 upper bits of gpio_dt...
Definition renesas-rz-gpio.h:29

◆ RZ_GPIO_IOLH_SHIFT

#define RZ_GPIO_IOLH_SHIFT   8U

RZ/A,G,V-specific GPIO Flags The pin driving ability flags are encoded in the 8 upper bits of gpio_dt_flags_t as follows:

  • Bit 8..9: Pin driving ability value
  • Bit 10: Digital Noise Filter ON/OFF
  • Bit 11..12: Digital Noise Filter Number value
  • Bit 13..14: Digital Noise Filter Clock Selection value example: gpio-consumer { out-gpios = <&port8 2 (GPIO_PULL_UP | RZ_GPIO_FILTER_SET(1, 3, 3))>; }; gpio-consumer { out-gpios = <&port8 2 (GPIO_PULL_UP | RZ_GPIO_IOLH_SET(2))>; };