Zephyr API Documentation 4.2.99
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stm32_clock_control.h
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1/*
2 * Copyright (c) 2016 Open-RnD Sp. z o.o.
3 * Copyright (c) 2016 BayLibre, SAS
4 * Copyright (c) 2017-2022 Linaro Limited.
5 * Copyright (c) 2017 RnDity Sp. z o.o.
6 * Copyright (c) 2023 STMicroelectronics
7 *
8 * SPDX-License-Identifier: Apache-2.0
9 */
10#ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_STM32_CLOCK_CONTROL_H_
11#define ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_STM32_CLOCK_CONTROL_H_
12
13#include <zephyr/drivers/clock_control.h>
14
15/* Retrieve the main system clock from DTS. */
16#define STM32_HCLK_FREQUENCY DT_PROP(DT_NODELABEL(rcc), clock_frequency)
17
18#if defined(CONFIG_SOC_SERIES_STM32C0X)
19#include <zephyr/dt-bindings/clock/stm32c0_clock.h>
20#elif defined(CONFIG_SOC_SERIES_STM32F0X)
21#include <zephyr/dt-bindings/clock/stm32f0_clock.h>
22#elif defined(CONFIG_SOC_SERIES_STM32F1X)
23#if defined(CONFIG_SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE)
24#include <zephyr/dt-bindings/clock/stm32f10x_clock.h>
25#else
26#include <zephyr/dt-bindings/clock/stm32f1_clock.h>
27#endif
28#elif defined(CONFIG_SOC_SERIES_STM32F3X)
29#include <zephyr/dt-bindings/clock/stm32f3_clock.h>
30#elif defined(CONFIG_SOC_SERIES_STM32F2X) || \
31 defined(CONFIG_SOC_SERIES_STM32F4X)
32#include <zephyr/dt-bindings/clock/stm32f4_clock.h>
33#include <zephyr/dt-bindings/clock/stm32f410_clock.h>
34#elif defined(CONFIG_SOC_SERIES_STM32F7X)
35#include <zephyr/dt-bindings/clock/stm32f7_clock.h>
36#elif defined(CONFIG_SOC_SERIES_STM32G0X)
37#include <zephyr/dt-bindings/clock/stm32g0_clock.h>
38#elif defined(CONFIG_SOC_SERIES_STM32G4X)
39#include <zephyr/dt-bindings/clock/stm32g4_clock.h>
40#elif defined(CONFIG_SOC_SERIES_STM32L0X)
41#include <zephyr/dt-bindings/clock/stm32l0_clock.h>
42#elif defined(CONFIG_SOC_SERIES_STM32L1X)
43#include <zephyr/dt-bindings/clock/stm32l1_clock.h>
44#elif defined(CONFIG_SOC_SERIES_STM32L4X)
45#include <zephyr/dt-bindings/clock/stm32l4_clock.h>
46#elif defined(CONFIG_SOC_SERIES_STM32L5X)
47#include <zephyr/dt-bindings/clock/stm32l5_clock.h>
48#elif defined(CONFIG_SOC_SERIES_STM32MP2X)
49#include <zephyr/dt-bindings/clock/stm32mp2_clock.h>
50#elif defined(CONFIG_SOC_SERIES_STM32WBX)
51#include <zephyr/dt-bindings/clock/stm32wb_clock.h>
52#elif defined(CONFIG_SOC_SERIES_STM32WB0X)
53#include <zephyr/dt-bindings/clock/stm32wb0_clock.h>
54#elif defined(CONFIG_SOC_SERIES_STM32WLX)
55#include <zephyr/dt-bindings/clock/stm32wl_clock.h>
56#elif defined(CONFIG_SOC_SERIES_STM32H5X)
57#include <zephyr/dt-bindings/clock/stm32h5_clock.h>
58#elif defined(CONFIG_SOC_SERIES_STM32H7X)
59#include <zephyr/dt-bindings/clock/stm32h7_clock.h>
60#elif defined(CONFIG_SOC_SERIES_STM32H7RSX)
61#include <zephyr/dt-bindings/clock/stm32h7rs_clock.h>
62#elif defined(CONFIG_SOC_SERIES_STM32MP13X)
63#include <zephyr/dt-bindings/clock/stm32mp13_clock.h>
64#elif defined(CONFIG_SOC_SERIES_STM32N6X)
65#include <zephyr/dt-bindings/clock/stm32n6_clock.h>
66#elif defined(CONFIG_SOC_SERIES_STM32U0X)
67#include <zephyr/dt-bindings/clock/stm32u0_clock.h>
68#elif defined(CONFIG_SOC_SERIES_STM32U3X)
69#include <zephyr/dt-bindings/clock/stm32u3_clock.h>
70#elif defined(CONFIG_SOC_SERIES_STM32U5X)
71#include <zephyr/dt-bindings/clock/stm32u5_clock.h>
72#elif defined(CONFIG_SOC_SERIES_STM32WBAX)
73#include <zephyr/dt-bindings/clock/stm32wba_clock.h>
74#else
75#include <zephyr/dt-bindings/clock/stm32_clock.h>
76#endif
77
79#define STM32_CLOCK_CONTROL_NODE DT_NODELABEL(rcc)
80
82
83#define STM32_AHB_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb_prescaler)
84#define STM32_APB1_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb1_prescaler)
85#define STM32_APB2_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb2_prescaler)
86#define STM32_APB3_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb3_prescaler)
87#define STM32_APB4_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb4_prescaler)
88#define STM32_APB5_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb5_prescaler)
89#define STM32_APB7_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb7_prescaler)
90#define STM32_AHB3_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb3_prescaler)
91#define STM32_AHB4_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb4_prescaler)
92#define STM32_AHB5_PRESCALER DT_PROP_OR(DT_NODELABEL(rcc), ahb5_prescaler, 1)
93#define STM32_CPU1_PRESCALER DT_PROP(DT_NODELABEL(rcc), cpu1_prescaler)
94#define STM32_CPU2_PRESCALER DT_PROP(DT_NODELABEL(rcc), cpu2_prescaler)
95
96#if DT_NODE_HAS_PROP(DT_NODELABEL(rcc), ahb_prescaler)
97#define STM32_CORE_PRESCALER STM32_AHB_PRESCALER
98#elif DT_NODE_HAS_PROP(DT_NODELABEL(rcc), cpu1_prescaler)
99#define STM32_CORE_PRESCALER STM32_CPU1_PRESCALER
100#endif
101
102#if DT_NODE_HAS_PROP(DT_NODELABEL(rcc), ahb3_prescaler)
103#define STM32_FLASH_PRESCALER STM32_AHB3_PRESCALER
104#elif DT_NODE_HAS_PROP(DT_NODELABEL(rcc), ahb4_prescaler)
105#define STM32_FLASH_PRESCALER STM32_AHB4_PRESCALER
106#else
107#define STM32_FLASH_PRESCALER STM32_CORE_PRESCALER
108#endif
109
110#define STM32_ADC_PRESCALER DT_PROP(DT_NODELABEL(rcc), adc_prescaler)
111#define STM32_ADC12_PRESCALER DT_PROP(DT_NODELABEL(rcc), adc12_prescaler)
112#define STM32_ADC34_PRESCALER DT_PROP(DT_NODELABEL(rcc), adc34_prescaler)
113
114#define STM32_TIMER_PRESCALER DT_PROP(DT_NODELABEL(rcc), timpre)
115
117#if defined(CONFIG_SOC_SERIES_STM32H7RSX)
118#define STM32_D1CPRE DT_PROP(DT_NODELABEL(rcc), dcpre)
119#define STM32_HPRE DT_PROP(DT_NODELABEL(rcc), hpre)
120#define STM32_PPRE1 DT_PROP(DT_NODELABEL(rcc), ppre1)
121#define STM32_PPRE2 DT_PROP(DT_NODELABEL(rcc), ppre2)
122#define STM32_PPRE4 DT_PROP(DT_NODELABEL(rcc), ppre4)
123#define STM32_PPRE5 DT_PROP(DT_NODELABEL(rcc), ppre5)
124#else
125#define STM32_D1CPRE DT_PROP(DT_NODELABEL(rcc), d1cpre)
126#define STM32_HPRE DT_PROP(DT_NODELABEL(rcc), hpre)
127#define STM32_D2PPRE1 DT_PROP(DT_NODELABEL(rcc), d2ppre1)
128#define STM32_D2PPRE2 DT_PROP(DT_NODELABEL(rcc), d2ppre2)
129#define STM32_D1PPRE DT_PROP(DT_NODELABEL(rcc), d1ppre)
130#define STM32_D3PPRE DT_PROP(DT_NODELABEL(rcc), d3ppre)
131#endif /* CONFIG_SOC_SERIES_STM32H7RSX */
132
134#define STM32_AHB5_DIV DT_PROP(DT_NODELABEL(rcc), ahb5_div)
135
136#define DT_RCC_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(rcc))
137
138/* To enable use of IS_ENABLED utility macro, these symbols
139 * should not be defined directly using DT_SAME_NODE.
140 */
141#if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(pll))
142#define STM32_SYSCLK_SRC_PLL 1
143#endif
144#if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
145#define STM32_SYSCLK_SRC_HSI 1
146#endif
147#if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
148#define STM32_SYSCLK_SRC_HSE 1
149#endif
150#if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
151#define STM32_SYSCLK_SRC_MSI 1
152#endif
153#if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_msis))
154#define STM32_SYSCLK_SRC_MSIS 1
155#endif
156#if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_csi))
157#define STM32_SYSCLK_SRC_CSI 1
158#endif
159#if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(ic2))
160#define STM32_SYSCLK_SRC_IC2 1
161#endif
162
163#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(rcc), st_stm32n6_rcc, okay)
164#if (DT_SAME_NODE(DT_CLOCKS_CTLR_BY_IDX(DT_NODELABEL(cpusw), 0), DT_NODELABEL(rcc)))
165#if (DT_CLOCKS_CELL_BY_IDX(DT_NODELABEL(cpusw), 0, bus) == STM32_SRC_HSI)
166#define STM32_CPUCLK_SRC_HSI 1
167#elif (DT_CLOCKS_CELL_BY_IDX(DT_NODELABEL(cpusw), 0, bus) == STM32_SRC_MSI)
168#define STM32_CPUCLK_SRC_MSI 1
169#elif (DT_CLOCKS_CELL_BY_IDX(DT_NODELABEL(cpusw), 0, bus) == STM32_SRC_HSE)
170#define STM32_CPUCLK_SRC_HSE 1
171#elif (DT_CLOCKS_CELL_BY_IDX(DT_NODELABEL(cpusw), 0, bus) == STM32_SRC_IC1)
172#define STM32_CPUCLK_SRC_IC1 1
173#endif
174#endif /* cpusw clk source is rcc */
175
176#define STM32_TIMG_PRESCALER DT_PROP(DT_NODELABEL(rcc), timg_prescaler)
177#endif /* rcc node compatible st_stm32n6_rcc and okay */
178
180
181#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f2_pll_clock, okay) || \
182 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f4_pll_clock, okay) || \
183 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f7_pll_clock, okay) || \
184 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g0_pll_clock, okay) || \
185 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g4_pll_clock, okay) || \
186 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l4_pll_clock, okay) || \
187 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32u0_pll_clock, okay) || \
188 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32u5_pll_clock, okay) || \
189 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wb_pll_clock, okay) || \
190 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wba_pll_clock, okay) || \
191 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32h7_pll_clock, okay) || \
192 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32h7rs_pll_clock, okay) || \
193 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32mp13_pll_clock, okay)
194#define STM32_PLL_ENABLED 1
195#define STM32_PLL_M_DIVISOR DT_PROP(DT_NODELABEL(pll), div_m)
196#define STM32_PLL_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul_n)
197#define STM32_PLL_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_p)
198#define STM32_PLL_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_p, 1)
199#define STM32_PLL_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_q)
200#define STM32_PLL_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_q, 1)
201#define STM32_PLL_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_r)
202#define STM32_PLL_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_r, 1)
203#define STM32_PLL_S_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_s)
204#define STM32_PLL_S_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_s, 1)
205#define STM32_PLL_FRACN_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), fracn)
206#define STM32_PLL_FRACN_VALUE DT_PROP_OR(DT_NODELABEL(pll), fracn, 1)
207#endif
208
209#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(plli2s), st_stm32f4_plli2s_clock, okay)
210#define STM32_PLLI2S_ENABLED 1
211#define STM32_PLLI2S_M_DIVISOR STM32_PLL_M_DIVISOR
212#define STM32_PLLI2S_N_MULTIPLIER DT_PROP(DT_NODELABEL(plli2s), mul_n)
213#define STM32_PLLI2S_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(plli2s), div_r)
214#define STM32_PLLI2S_R_DIVISOR DT_PROP_OR(DT_NODELABEL(plli2s), div_r, 1)
215#endif
216
217#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(plli2s), st_stm32f411_plli2s_clock, okay)
218#define STM32_PLLI2S_ENABLED 1
219#define STM32_PLLI2S_M_DIVISOR DT_PROP(DT_NODELABEL(plli2s), div_m)
220#define STM32_PLLI2S_N_MULTIPLIER DT_PROP(DT_NODELABEL(plli2s), mul_n)
221#define STM32_PLLI2S_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(plli2s), div_q)
222#define STM32_PLLI2S_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(plli2s), div_q, 1)
223#define STM32_PLLI2S_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(plli2s), div_r)
224#define STM32_PLLI2S_R_DIVISOR DT_PROP_OR(DT_NODELABEL(plli2s), div_r, 1)
225#endif
226
227#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pllsai), st_stm32fx_pllsai_clock, okay)
228#define STM32_PLLSAI_ENABLED 1
229#define STM32_PLLSAI_M_DIVISOR DT_PROP(DT_NODELABEL(pllsai), div_m)
230#define STM32_PLLSAI_N_MULTIPLIER DT_PROP(DT_NODELABEL(pllsai), mul_n)
231#define STM32_PLLSAI_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai), div_p)
232#define STM32_PLLSAI_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai), div_p, 1)
233#define STM32_PLLSAI_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai), div_q)
234#define STM32_PLLSAI_DIVQ_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai), div_divq)
235#if (STM32_PLLSAI_Q_ENABLED && !STM32_PLLSAI_DIVQ_ENABLED) || \
236 (!STM32_PLLSAI_Q_ENABLED && STM32_PLLSAI_DIVQ_ENABLED)
237#error "On STM32F4/STM32F7, both div_q and div_divq must be present if one of them is present"
238#endif
239#define STM32_PLLSAI_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai), div_q, 1)
240#define STM32_PLLSAI_DIVQ_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai), div_divq, 1)
241#define STM32_PLLSAI_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai), div_r)
242#define STM32_PLLSAI_DIVR_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai), div_divr)
243#if (STM32_PLLSAI_R_ENABLED && !STM32_PLLSAI_DIVR_ENABLED) || \
244 (!STM32_PLLSAI_R_ENABLED && STM32_PLLSAI_DIVR_ENABLED)
245#error "On STM32F4/STM32F7, both div_r and div_divr must be present if one of them is present"
246#endif
247#define STM32_PLLSAI_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai), div_r, 1)
248#define STM32_PLLSAI_DIVR_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai), div_divr, 1)
249#endif
250
251#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pllsai1), st_stm32l4_pllsai_clock, okay)
252#define STM32_PLLSAI1_ENABLED 1
253#define STM32_PLLSAI1_M_DIVISOR DT_PROP(DT_NODELABEL(pllsai1), div_m)
254#define STM32_PLLSAI1_N_MULTIPLIER DT_PROP(DT_NODELABEL(pllsai1), mul_n)
255#define STM32_PLLSAI1_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai1), div_p)
256#define STM32_PLLSAI1_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai1), div_p, 1)
257#define STM32_PLLSAI1_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai1), div_q)
258#define STM32_PLLSAI1_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai1), div_q, 1)
259#define STM32_PLLSAI1_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai1), div_r)
260#define STM32_PLLSAI1_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai1), div_r, 1)
261#endif
262
263#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pllsai2), st_stm32l4_pllsai_clock, okay)
264#define STM32_PLLSAI2_ENABLED 1
265#define STM32_PLLSAI2_M_DIVISOR DT_PROP(DT_NODELABEL(pllsai2), div_m)
266#define STM32_PLLSAI2_N_MULTIPLIER DT_PROP(DT_NODELABEL(pllsai2), mul_n)
267#define STM32_PLLSAI2_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai2), div_p)
268#define STM32_PLLSAI2_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai2), div_p, 1)
269#define STM32_PLLSAI2_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai2), div_q)
270#define STM32_PLLSAI2_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai2), div_q, 1)
271#define STM32_PLLSAI2_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai2), div_r)
272#define STM32_PLLSAI2_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai2), div_r, 1)
273#define STM32_PLLSAI2_DIVR_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai2), div_divr)
274#define STM32_PLLSAI2_DIVR_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai2), div_divr, 1)
275#endif
276
277#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32u5_pll_clock, okay) || \
278 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32h7_pll_clock, okay) || \
279 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32h7rs_pll_clock, okay) || \
280 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32mp13_pll_clock, okay)
281#define STM32_PLL2_ENABLED 1
282#define STM32_PLL2_M_DIVISOR DT_PROP(DT_NODELABEL(pll2), div_m)
283#define STM32_PLL2_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll2), mul_n)
284#define STM32_PLL2_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_p)
285#define STM32_PLL2_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_p, 1)
286#define STM32_PLL2_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_q)
287#define STM32_PLL2_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_q, 1)
288#define STM32_PLL2_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_r)
289#define STM32_PLL2_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_r, 1)
290#define STM32_PLL2_S_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_s)
291#define STM32_PLL2_S_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_s, 1)
292#define STM32_PLL2_T_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_t)
293#define STM32_PLL2_T_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_t, 1)
294#define STM32_PLL2_FRACN_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), fracn)
295#define STM32_PLL2_FRACN_VALUE DT_PROP_OR(DT_NODELABEL(pll2), fracn, 1)
296#endif
297
298#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32h7_pll_clock, okay) || \
299 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32u5_pll_clock, okay) || \
300 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32h7rs_pll_clock, okay) || \
301 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32mp13_pll_clock, okay)
302#define STM32_PLL3_ENABLED 1
303#define STM32_PLL3_M_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_m)
304#define STM32_PLL3_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll3), mul_n)
305#define STM32_PLL3_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_p)
306#define STM32_PLL3_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pll3), div_p, 1)
307#define STM32_PLL3_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_q)
308#define STM32_PLL3_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pll3), div_q, 1)
309#define STM32_PLL3_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_r)
310#define STM32_PLL3_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pll3), div_r, 1)
311#define STM32_PLL3_S_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_s)
312#define STM32_PLL3_S_DIVISOR DT_PROP_OR(DT_NODELABEL(pll3), div_s, 1)
313#define STM32_PLL3_FRACN_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), fracn)
314#define STM32_PLL3_FRACN_VALUE DT_PROP_OR(DT_NODELABEL(pll3), fracn, 1)
315#endif
316
317#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll4), st_stm32mp13_pll_clock, okay)
318#define STM32_PLL4_ENABLED 1
319#define STM32_PLL4_M_DIVISOR DT_PROP(DT_NODELABEL(pll4), div_m)
320#define STM32_PLL4_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll4), mul_n)
321#define STM32_PLL4_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll4), div_p)
322#define STM32_PLL4_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pll4), div_p, 1)
323#define STM32_PLL4_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll4), div_q)
324#define STM32_PLL4_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pll4), div_q, 1)
325#define STM32_PLL4_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll4), div_r)
326#define STM32_PLL4_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pll4), div_r, 1)
327#define STM32_PLL4_FRACN_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll4), fracn)
328#define STM32_PLL4_FRACN_VALUE DT_PROP_OR(DT_NODELABEL(pll4), fracn, 1)
329#endif
330
331#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f1_pll_clock, okay)
332#define STM32_PLL_ENABLED 1
333#define STM32_PLL_XTPRE DT_PROP(DT_NODELABEL(pll), xtpre)
334#define STM32_PLL_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul)
335#define STM32_PLL_USBPRE DT_PROP(DT_NODELABEL(pll), usbpre)
336#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f0_pll_clock, okay) || \
337 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f100_pll_clock, okay) || \
338 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f105_pll_clock, okay)
339#define STM32_PLL_ENABLED 1
340#define STM32_PLL_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul)
341#define STM32_PLL_PREDIV DT_PROP(DT_NODELABEL(pll), prediv)
342#define STM32_PLL_USBPRE DT_PROP(DT_NODELABEL(pll), otgfspre)
343#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l0_pll_clock, okay)
344#define STM32_PLL_ENABLED 1
345#define STM32_PLL_DIVISOR DT_PROP(DT_NODELABEL(pll), div)
346#define STM32_PLL_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul)
347#endif
348
349#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32f105_pll2_clock, okay)
350#define STM32_PLL2_ENABLED 1
351#define STM32_PLL2_MULTIPLIER DT_PROP(DT_NODELABEL(pll2), mul)
352#define STM32_PLL2_PREDIV DT_PROP(DT_NODELABEL(pll2), prediv)
353#endif
354
355#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll1), st_stm32n6_pll_clock, okay)
356#define STM32_PLL1_ENABLED 1
357#define STM32_PLL1_M_DIVISOR DT_PROP(DT_NODELABEL(pll1), div_m)
358#define STM32_PLL1_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll1), mul_n)
359#define STM32_PLL1_P1_DIVISOR DT_PROP(DT_NODELABEL(pll1), div_p1)
360#define STM32_PLL1_P2_DIVISOR DT_PROP(DT_NODELABEL(pll1), div_p2)
361#endif
362
363#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32n6_pll_clock, okay)
364#define STM32_PLL2_ENABLED 1
365#define STM32_PLL2_M_DIVISOR DT_PROP(DT_NODELABEL(pll2), div_m)
366#define STM32_PLL2_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll2), mul_n)
367#define STM32_PLL2_P1_DIVISOR DT_PROP(DT_NODELABEL(pll2), div_p1)
368#define STM32_PLL2_P2_DIVISOR DT_PROP(DT_NODELABEL(pll2), div_p2)
369#endif
370
371#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32n6_pll_clock, okay)
372#define STM32_PLL3_ENABLED 1
373#define STM32_PLL3_M_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_m)
374#define STM32_PLL3_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll3), mul_n)
375#define STM32_PLL3_P1_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_p1)
376#define STM32_PLL3_P2_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_p2)
377#endif
378
379#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll4), st_stm32n6_pll_clock, okay)
380#define STM32_PLL4_ENABLED 1
381#define STM32_PLL4_M_DIVISOR DT_PROP(DT_NODELABEL(pll4), div_m)
382#define STM32_PLL4_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll4), mul_n)
383#define STM32_PLL4_P1_DIVISOR DT_PROP(DT_NODELABEL(pll4), div_p1)
384#define STM32_PLL4_P2_DIVISOR DT_PROP(DT_NODELABEL(pll4), div_p2)
385#endif
386
388#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pll)) && \
389 DT_NODE_HAS_PROP(DT_NODELABEL(pll), clocks)
390#define DT_PLL_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll))
391#if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
392#define STM32_PLL_SRC_MSI 1
393#endif
394#if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_msis))
395#define STM32_PLL_SRC_MSIS 1
396#endif
397#if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
398#define STM32_PLL_SRC_HSI 1
399#endif
400#if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_csi))
401#define STM32_PLL_SRC_CSI 1
402#endif
403#if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
404#define STM32_PLL_SRC_HSE 1
405#endif
406#if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(pll2))
407#define STM32_PLL_SRC_PLL2 1
408#endif
409
410#endif
411
413#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pll2)) && \
414 DT_NODE_HAS_PROP(DT_NODELABEL(pll2), clocks)
415#define DT_PLL2_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll2))
416#if DT_SAME_NODE(DT_PLL2_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
417#define STM32_PLL2_SRC_MSI 1
418#endif
419#if DT_SAME_NODE(DT_PLL2_CLOCKS_CTRL, DT_NODELABEL(clk_msis))
420#define STM32_PLL2_SRC_MSIS 1
421#endif
422#if DT_SAME_NODE(DT_PLL2_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
423#define STM32_PLL2_SRC_HSI 1
424#endif
425#if DT_SAME_NODE(DT_PLL2_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
426#define STM32_PLL2_SRC_HSE 1
427#endif
428
429#endif
430
432#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pll3)) && \
433 DT_NODE_HAS_PROP(DT_NODELABEL(pll3), clocks)
434#define DT_PLL3_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll3))
435#if DT_SAME_NODE(DT_PLL3_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
436#define STM32_PLL3_SRC_MSI 1
437#endif
438#if DT_SAME_NODE(DT_PLL3_CLOCKS_CTRL, DT_NODELABEL(clk_msis))
439#define STM32_PLL3_SRC_MSIS 1
440#endif
441#if DT_SAME_NODE(DT_PLL3_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
442#define STM32_PLL3_SRC_HSI 1
443#endif
444#if DT_SAME_NODE(DT_PLL3_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
445#define STM32_PLL3_SRC_HSE 1
446#endif
447
448#endif
449
451#if DT_NODE_HAS_STATUS(DT_NODELABEL(pll4), okay) && \
452 DT_NODE_HAS_PROP(DT_NODELABEL(pll4), clocks)
453#define DT_PLL4_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll4))
454#if DT_SAME_NODE(DT_PLL4_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
455#define STM32_PLL4_SRC_MSI 1
456#endif
457#if DT_SAME_NODE(DT_PLL4_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
458#define STM32_PLL4_SRC_HSI 1
459#endif
460#if DT_SAME_NODE(DT_PLL4_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
461#define STM32_PLL4_SRC_HSE 1
462#endif
463
464#endif
465
467#if DT_NODE_HAS_STATUS(DT_NODELABEL(pllsai), okay) && \
468 DT_NODE_HAS_PROP(DT_NODELABEL(pllsai), clocks)
469#define DT_PLLSAI_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pllsai))
470#if DT_SAME_NODE(DT_PLLSAI_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
471#define STM32_PLLSAI_SRC_HSI 1
472#endif
473#if DT_SAME_NODE(DT_PLLSAI_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
474#define STM32_PLLSAI_SRC_HSE 1
475#endif
476
477#endif
478
480#if DT_NODE_HAS_STATUS(DT_NODELABEL(pllsai1), okay) && \
481 DT_NODE_HAS_PROP(DT_NODELABEL(pllsai1), clocks)
482#define DT_PLLSAI1_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pllsai1))
483#if DT_SAME_NODE(DT_PLLSAI1_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
484#define STM32_PLLSAI1_SRC_MSI 1
485#endif
486#if DT_SAME_NODE(DT_PLLSAI1_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
487#define STM32_PLLSAI1_SRC_HSI 1
488#endif
489#if DT_SAME_NODE(DT_PLLSAI1_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
490#define STM32_PLLSAI1_SRC_HSE 1
491#endif
492
493#endif
494
496#if DT_NODE_HAS_STATUS(DT_NODELABEL(pllsai2), okay) && \
497 DT_NODE_HAS_PROP(DT_NODELABEL(pllsai2), clocks)
498#define DT_PLLSAI2_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pllsai2))
499#if DT_SAME_NODE(DT_PLLSAI2_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
500#define STM32_PLLSAI2_SRC_MSI 1
501#endif
502#if DT_SAME_NODE(DT_PLLSAI2_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
503#define STM32_PLLSAI2_SRC_HSI 1
504#endif
505#if DT_SAME_NODE(DT_PLLSAI2_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
506#define STM32_PLLSAI2_SRC_HSE 1
507#endif
508
509#endif
510
511/* On STM32F4 series - PLL and PLLSAI share the same source */
512#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f4_pll_clock, okay) && \
513 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pllsai), st_stm32fx_pllsai_clock, okay) && \
514 !DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_PLLSAI_CLOCKS_CTRL)
515#error "On STM32F4 series, PLL and PLLSAI must have the same source"
516#endif
517
518/* On STM32F7 series - PLL and PLLSAI share the same source */
519#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f7_pll_clock, okay) && \
520 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pllsai), st_stm32fx_pllsai_clock, okay) && \
521 !DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_PLLSAI_CLOCKS_CTRL)
522#error "On STM32F7 series, PLL and PLLSAI must have the same source"
523#endif
524
525/* On STM32L4 series - PLL / PLLSAI1 and PLLSAI2 shared same source */
526#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l4_pll_clock, okay) && \
527 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pllsai1), st_stm32l4_pllsai_clock, okay) && \
528 !DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_PLLSAI1_CLOCKS_CTRL)
529#error "On STM32L4 series, PLL / PLLSAI1 must have the same source"
530#endif
531#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l4_pll_clock, okay) && \
532 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pllsai2), st_stm32l4_pllsai_clock, okay) && \
533 !DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_PLLSAI2_CLOCKS_CTRL)
534#error "On STM32L4 series, PLL / PLLSAI2 must have the same source"
535#endif
536#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pllsai1), st_stm32l4_pllsai_clock, okay) && \
537 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pllsai2), st_stm32l4_pllsai_clock, okay) && \
538 !DT_SAME_NODE(DT_PLLSAI1_CLOCKS_CTRL, DT_PLLSAI2_CLOCKS_CTRL)
539#error "On STM32L4 series, PLLSAI1 / PLLSAI2 must have the same source"
540#endif
541
543
544#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lse), fixed_clock, okay)
545#define STM32_LSE_ENABLED 1
546#define STM32_LSE_FREQ DT_PROP(DT_NODELABEL(clk_lse), clock_frequency)
547#define STM32_LSE_DRIVING 0
548#define STM32_LSE_BYPASS DT_PROP(DT_NODELABEL(clk_lse), lse_bypass)
549#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lse), st_stm32_lse_clock, okay)
550#define STM32_LSE_ENABLED 1
551#define STM32_LSE_FREQ DT_PROP(DT_NODELABEL(clk_lse), clock_frequency)
552#define STM32_LSE_DRIVING DT_PROP(DT_NODELABEL(clk_lse), driving_capability)
553#define STM32_LSE_BYPASS DT_PROP(DT_NODELABEL(clk_lse), lse_bypass)
554#else
555#define STM32_LSE_ENABLED 0
556#define STM32_LSE_FREQ 0
557#define STM32_LSE_DRIVING 0
558#define STM32_LSE_BYPASS 0
559#endif
560
561#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32_msi_clock, okay) || \
562 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32l0_msi_clock, okay)
563#define STM32_MSI_ENABLED 1
564#define STM32_MSI_RANGE DT_PROP(DT_NODELABEL(clk_msi), msi_range)
565#endif
566
567#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32_msi_clock, okay)
568#define STM32_MSI_ENABLED 1
569#define STM32_MSI_PLL_MODE DT_PROP(DT_NODELABEL(clk_msi), msi_pll_mode)
570#endif
571
572#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msis), st_stm32u5_msi_clock, okay) || \
573 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msis), st_stm32u3_msi_clock, okay)
574#define STM32_MSIS_ENABLED 1
575#define STM32_MSIS_RANGE DT_PROP(DT_NODELABEL(clk_msis), msi_range)
576#define STM32_MSIS_PLL_MODE DT_PROP(DT_NODELABEL(clk_msis), msi_pll_mode)
577#else
578#define STM32_MSIS_ENABLED 0
579#define STM32_MSIS_RANGE 0
580#define STM32_MSIS_PLL_MODE 0
581#endif
582
583#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msik), st_stm32u5_msi_clock, okay) || \
584 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msik), st_stm32u3_msi_clock, okay)
585#define STM32_MSIK_ENABLED 1
586#define STM32_MSIK_RANGE DT_PROP(DT_NODELABEL(clk_msik), msi_range)
587#define STM32_MSIK_PLL_MODE DT_PROP(DT_NODELABEL(clk_msik), msi_pll_mode)
588#else
589#define STM32_MSIK_ENABLED 0
590#define STM32_MSIK_RANGE 0
591#define STM32_MSIK_PLL_MODE 0
592#endif
593
594#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_csi), fixed_clock, okay)
595#define STM32_CSI_ENABLED 1
596#define STM32_CSI_FREQ DT_PROP(DT_NODELABEL(clk_csi), clock_frequency)
597#else
598#define STM32_CSI_FREQ 0
599#endif
600
601#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lsi), fixed_clock, okay)
602#define STM32_LSI_ENABLED 1
603#define STM32_LSI_FREQ DT_PROP(DT_NODELABEL(clk_lsi), clock_frequency)
604#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lsi1), fixed_clock, okay)
605#define STM32_LSI_ENABLED 1
606#define STM32_LSI_FREQ DT_PROP(DT_NODELABEL(clk_lsi1), clock_frequency)
607#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lsi2), fixed_clock, okay)
608#define STM32_LSI_ENABLED 1
609#define STM32_LSI_FREQ DT_PROP(DT_NODELABEL(clk_lsi2), clock_frequency)
610#else
611#define STM32_LSI_FREQ 0
612#endif
613
614#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), fixed_clock, okay)
615#define STM32_HSI_DIV_ENABLED 0
616#define STM32_HSI_ENABLED 1
617#define STM32_HSI_FREQ DT_PROP(DT_NODELABEL(clk_hsi), clock_frequency)
618#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32h7_hsi_clock, okay) \
619 || DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32l0_hsi_clock, okay) \
620 || DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32g0_hsi_clock, okay) \
621 || DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32c0_hsi_clock, okay) \
622 || DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32n6_hsi_clock, okay)
623#define STM32_HSI_DIV_ENABLED 1
624#define STM32_HSI_ENABLED 1
625#define STM32_HSI_DIVISOR DT_PROP(DT_NODELABEL(clk_hsi), hsi_div)
626#define STM32_HSI_FREQ DT_PROP(DT_NODELABEL(clk_hsi), clock_frequency)
627#else
628#define STM32_HSI_DIV_ENABLED 0
629#define STM32_HSI_DIVISOR 1
630#define STM32_HSI_FREQ 0
631#endif
632
633#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), fixed_clock, okay)
634#define STM32_HSE_ENABLED 1
635#define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency)
636#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32_hse_clock, okay)
637#define STM32_HSE_ENABLED 1
638#define STM32_HSE_BYPASS DT_PROP(DT_NODELABEL(clk_hse), hse_bypass)
639#define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency)
640#define STM32_HSE_CSS DT_PROP(DT_NODELABEL(clk_hse), css_enabled)
641#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32wl_hse_clock, okay)
642#define STM32_HSE_ENABLED 1
643#define STM32_HSE_TCXO DT_PROP(DT_NODELABEL(clk_hse), hse_tcxo)
644#define STM32_HSE_DIV2 DT_PROP(DT_NODELABEL(clk_hse), hse_div2)
645#define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency)
646#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32wba_hse_clock, okay)
647#define STM32_HSE_ENABLED 1
648#define STM32_HSE_DIV2 DT_PROP(DT_NODELABEL(clk_hse), hse_div2)
649#define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency)
650#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32n6_hse_clock, okay)
651#define STM32_HSE_ENABLED 1
652#define STM32_HSE_BYPASS DT_PROP(DT_NODELABEL(clk_hse), hse_bypass)
653#define STM32_HSE_DIV2 DT_PROP(DT_NODELABEL(clk_hse), hse_div2)
654#define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency)
655#else
656#define STM32_HSE_FREQ 0
657#endif
658
659#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi48), fixed_clock, okay)
660#define STM32_HSI48_ENABLED 1
661#define STM32_HSI48_FREQ DT_PROP(DT_NODELABEL(clk_hsi48), clock_frequency)
662#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi48), st_stm32_hsi48_clock, okay)
663#define STM32_HSI48_ENABLED 1
664#define STM32_HSI48_FREQ DT_PROP(DT_NODELABEL(clk_hsi48), clock_frequency)
665#define STM32_HSI48_CRS_USB_SOF DT_PROP(DT_NODELABEL(clk_hsi48), crs_usb_sof)
666#endif
667
668#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(perck), st_stm32_clock_mux, okay)
669#define STM32_CKPER_ENABLED 1
670#endif
671
672#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(cpusw), st_stm32_clock_mux, okay)
673#define STM32_CPUSW_ENABLED 1
674#endif
675
676#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic1), st_stm32n6_ic_clock_mux, okay)
677#define STM32_IC1_ENABLED 1
678#define STM32_IC1_PLL_SRC DT_PROP(DT_NODELABEL(ic1), pll_src)
679#define STM32_IC1_DIV DT_PROP(DT_NODELABEL(ic1), ic_div)
680#endif
681
682#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic2), st_stm32n6_ic_clock_mux, okay)
683#define STM32_IC2_ENABLED 1
684#define STM32_IC2_PLL_SRC DT_PROP(DT_NODELABEL(ic2), pll_src)
685#define STM32_IC2_DIV DT_PROP(DT_NODELABEL(ic2), ic_div)
686#endif
687
688#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic3), st_stm32n6_ic_clock_mux, okay)
689#define STM32_IC3_ENABLED 1
690#define STM32_IC3_PLL_SRC DT_PROP(DT_NODELABEL(ic3), pll_src)
691#define STM32_IC3_DIV DT_PROP(DT_NODELABEL(ic3), ic_div)
692#endif
693
694#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic4), st_stm32n6_ic_clock_mux, okay)
695#define STM32_IC4_ENABLED 1
696#define STM32_IC4_PLL_SRC DT_PROP(DT_NODELABEL(ic4), pll_src)
697#define STM32_IC4_DIV DT_PROP(DT_NODELABEL(ic4), ic_div)
698#endif
699
700#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic5), st_stm32n6_ic_clock_mux, okay)
701#define STM32_IC5_ENABLED 1
702#define STM32_IC5_PLL_SRC DT_PROP(DT_NODELABEL(ic5), pll_src)
703#define STM32_IC5_DIV DT_PROP(DT_NODELABEL(ic5), ic_div)
704#endif
705
706#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic6), st_stm32n6_ic_clock_mux, okay)
707#define STM32_IC6_ENABLED 1
708#define STM32_IC6_PLL_SRC DT_PROP(DT_NODELABEL(ic6), pll_src)
709#define STM32_IC6_DIV DT_PROP(DT_NODELABEL(ic6), ic_div)
710#endif
711
712#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic7), st_stm32n6_ic_clock_mux, okay)
713#define STM32_IC7_ENABLED 1
714#define STM32_IC7_PLL_SRC DT_PROP(DT_NODELABEL(ic7), pll_src)
715#define STM32_IC7_DIV DT_PROP(DT_NODELABEL(ic7), ic_div)
716#endif
717
718#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic8), st_stm32n6_ic_clock_mux, okay)
719#define STM32_IC8_ENABLED 1
720#define STM32_IC8_PLL_SRC DT_PROP(DT_NODELABEL(ic8), pll_src)
721#define STM32_IC8_DIV DT_PROP(DT_NODELABEL(ic8), ic_div)
722#endif
723
724#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic9), st_stm32n6_ic_clock_mux, okay)
725#define STM32_IC9_ENABLED 1
726#define STM32_IC9_PLL_SRC DT_PROP(DT_NODELABEL(ic9), pll_src)
727#define STM32_IC9_DIV DT_PROP(DT_NODELABEL(ic9), ic_div)
728#endif
729
730#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic10), st_stm32n6_ic_clock_mux, okay)
731#define STM32_IC10_ENABLED 1
732#define STM32_IC10_PLL_SRC DT_PROP(DT_NODELABEL(ic10), pll_src)
733#define STM32_IC10_DIV DT_PROP(DT_NODELABEL(ic10), ic_div)
734#endif
735
736#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic11), st_stm32n6_ic_clock_mux, okay)
737#define STM32_IC11_ENABLED 1
738#define STM32_IC11_PLL_SRC DT_PROP(DT_NODELABEL(ic11), pll_src)
739#define STM32_IC11_DIV DT_PROP(DT_NODELABEL(ic11), ic_div)
740#endif
741
742#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic12), st_stm32n6_ic_clock_mux, okay)
743#define STM32_IC12_ENABLED 1
744#define STM32_IC12_PLL_SRC DT_PROP(DT_NODELABEL(ic12), pll_src)
745#define STM32_IC12_DIV DT_PROP(DT_NODELABEL(ic12), ic_div)
746#endif
747
748#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic13), st_stm32n6_ic_clock_mux, okay)
749#define STM32_IC13_ENABLED 1
750#define STM32_IC13_PLL_SRC DT_PROP(DT_NODELABEL(ic13), pll_src)
751#define STM32_IC13_DIV DT_PROP(DT_NODELABEL(ic13), ic_div)
752#endif
753
754#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic14), st_stm32n6_ic_clock_mux, okay)
755#define STM32_IC14_ENABLED 1
756#define STM32_IC14_PLL_SRC DT_PROP(DT_NODELABEL(ic14), pll_src)
757#define STM32_IC14_DIV DT_PROP(DT_NODELABEL(ic14), ic_div)
758#endif
759
760#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic15), st_stm32n6_ic_clock_mux, okay)
761#define STM32_IC15_ENABLED 1
762#define STM32_IC15_PLL_SRC DT_PROP(DT_NODELABEL(ic15), pll_src)
763#define STM32_IC15_DIV DT_PROP(DT_NODELABEL(ic15), ic_div)
764#endif
765
766#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic16), st_stm32n6_ic_clock_mux, okay)
767#define STM32_IC16_ENABLED 1
768#define STM32_IC16_PLL_SRC DT_PROP(DT_NODELABEL(ic16), pll_src)
769#define STM32_IC16_DIV DT_PROP(DT_NODELABEL(ic16), ic_div)
770#endif
771
772#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic17), st_stm32n6_ic_clock_mux, okay)
773#define STM32_IC17_ENABLED 1
774#define STM32_IC17_PLL_SRC DT_PROP(DT_NODELABEL(ic17), pll_src)
775#define STM32_IC17_DIV DT_PROP(DT_NODELABEL(ic17), ic_div)
776#endif
777
778#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic18), st_stm32n6_ic_clock_mux, okay)
779#define STM32_IC18_ENABLED 1
780#define STM32_IC18_PLL_SRC DT_PROP(DT_NODELABEL(ic18), pll_src)
781#define STM32_IC18_DIV DT_PROP(DT_NODELABEL(ic18), ic_div)
782#endif
783
784#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic19), st_stm32n6_ic_clock_mux, okay)
785#define STM32_IC19_ENABLED 1
786#define STM32_IC19_PLL_SRC DT_PROP(DT_NODELABEL(ic19), pll_src)
787#define STM32_IC19_DIV DT_PROP(DT_NODELABEL(ic19), ic_div)
788#endif
789
790#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic20), st_stm32n6_ic_clock_mux, okay)
791#define STM32_IC20_ENABLED 1
792#define STM32_IC20_PLL_SRC DT_PROP(DT_NODELABEL(ic20), pll_src)
793#define STM32_IC20_DIV DT_PROP(DT_NODELABEL(ic20), ic_div)
794#endif
795
797
803
805
806#define STM32_CLOCK_INFO(clk_index, node_id) \
807 { \
808 .enr = DT_CLOCKS_CELL_BY_IDX(node_id, clk_index, bits), \
809 .bus = DT_CLOCKS_CELL_BY_IDX(node_id, clk_index, bus) & \
810 GENMASK(STM32_CLOCK_DIV_SHIFT - 1, 0), \
811 .div = DT_CLOCKS_CELL_BY_IDX(node_id, clk_index, bus) >> \
812 STM32_CLOCK_DIV_SHIFT, \
813 }
814#define STM32_DT_CLOCKS(node_id) \
815 { \
816 LISTIFY(DT_NUM_CLOCKS(node_id), \
817 STM32_CLOCK_INFO, (,), node_id) \
818 }
819
820#define STM32_DT_INST_CLOCKS(inst) \
821 STM32_DT_CLOCKS(DT_DRV_INST(inst))
822
823#define STM32_DOMAIN_CLOCK_INST_SUPPORT(inst) DT_INST_CLOCKS_HAS_IDX(inst, 1) ||
824#define STM32_DT_INST_DEV_DOMAIN_CLOCK_SUPPORT \
825 (DT_INST_FOREACH_STATUS_OKAY(STM32_DOMAIN_CLOCK_INST_SUPPORT) 0)
826
827#define STM32_DOMAIN_CLOCK_SUPPORT(id) DT_CLOCKS_HAS_IDX(DT_NODELABEL(id), 1) ||
828#define STM32_DT_DEV_DOMAIN_CLOCK_SUPPORT \
829 (DT_FOREACH_STATUS_OKAY(STM32_DOMAIN_CLOCK_SUPPORT) 0)
830
832
838#define STM32_DT_CLKSEL_REG_GET(clock) \
839 (((clock) >> STM32_DT_CLKSEL_REG_SHIFT) & STM32_DT_CLKSEL_REG_MASK)
840
846#define STM32_DT_CLKSEL_SHIFT_GET(clock) \
847 (((clock) >> STM32_DT_CLKSEL_SHIFT_SHIFT) & STM32_DT_CLKSEL_SHIFT_MASK)
848
854#define STM32_DT_CLKSEL_MASK_GET(clock) \
855 (((clock) >> STM32_DT_CLKSEL_MASK_SHIFT) & STM32_DT_CLKSEL_MASK_MASK)
856
862#define STM32_DT_CLKSEL_VAL_GET(clock) \
863 (((clock) >> STM32_DT_CLKSEL_VAL_SHIFT) & STM32_DT_CLKSEL_VAL_MASK)
864
865#if defined(STM32_HSE_CSS)
874void stm32_hse_css_callback(void);
875#endif
876
877#ifdef CONFIG_SOC_SERIES_STM32WB0X
882typedef void (*lsi_update_cb_t)(uint32_t new_lsi_frequency);
883
895int stm32wb0_register_lsi_update_callback(lsi_update_cb_t cb);
896#endif /* CONFIG_SOC_SERIES_STM32WB0X */
897
898#endif /* ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_STM32_CLOCK_CONTROL_H_ */
clock_control.h
Main header file for clock control driver API.
uint32_t
__UINT32_TYPE__ uint32_t
Definition stdint.h:90
stm32_clock.h
STM32_CLOCK_DIV_SHIFT
#define STM32_CLOCK_DIV_SHIFT
Definition stm32_clock.h:27
stm32c0_clock.h
stm32f0_clock.h
stm32f10x_clock.h
stm32f1_clock.h
stm32f3_clock.h
stm32f410_clock.h
stm32f4_clock.h
stm32f7_clock.h
stm32g0_clock.h
stm32g4_clock.h
stm32h5_clock.h
stm32h7_clock.h
stm32h7rs_clock.h
stm32l0_clock.h
stm32l1_clock.h
stm32l4_clock.h
stm32l5_clock.h
stm32mp13_clock.h
stm32mp2_clock.h
stm32n6_clock.h
stm32u0_clock.h
stm32u3_clock.h
stm32u5_clock.h
stm32wb0_clock.h
stm32wb_clock.h
stm32wba_clock.h
stm32wl_clock.h
stm32_pclken
Driver structure definition.
Definition stm32_clock_control.h:798
stm32_pclken::div
uint32_t div
Definition stm32_clock_control.h:800
stm32_pclken::bus
uint32_t bus
Definition stm32_clock_control.h:799
stm32_pclken::enr
uint32_t enr
Definition stm32_clock_control.h:801