Zephyr API Documentation 4.1.99
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stm32_clock_control.h
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1/*
2 * Copyright (c) 2016 Open-RnD Sp. z o.o.
3 * Copyright (c) 2016 BayLibre, SAS
4 * Copyright (c) 2017-2022 Linaro Limited.
5 * Copyright (c) 2017 RnDity Sp. z o.o.
6 * Copyright (c) 2023 STMicroelectronics
7 *
8 * SPDX-License-Identifier: Apache-2.0
9 */
10#ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_STM32_CLOCK_CONTROL_H_
11#define ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_STM32_CLOCK_CONTROL_H_
12
13#include <zephyr/drivers/clock_control.h>
14
15#if defined(CONFIG_SOC_SERIES_STM32C0X)
16#include <zephyr/dt-bindings/clock/stm32c0_clock.h>
17#elif defined(CONFIG_SOC_SERIES_STM32F0X)
18#include <zephyr/dt-bindings/clock/stm32f0_clock.h>
19#elif defined(CONFIG_SOC_SERIES_STM32F1X)
20#if defined(CONFIG_SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE)
21#include <zephyr/dt-bindings/clock/stm32f10x_clock.h>
22#else
23#include <zephyr/dt-bindings/clock/stm32f1_clock.h>
24#endif
25#elif defined(CONFIG_SOC_SERIES_STM32F3X)
26#include <zephyr/dt-bindings/clock/stm32f3_clock.h>
27#elif defined(CONFIG_SOC_SERIES_STM32F2X) || \
28 defined(CONFIG_SOC_SERIES_STM32F4X)
29#include <zephyr/dt-bindings/clock/stm32f4_clock.h>
30#include <zephyr/dt-bindings/clock/stm32f410_clock.h>
31#elif defined(CONFIG_SOC_SERIES_STM32F7X)
32#include <zephyr/dt-bindings/clock/stm32f7_clock.h>
33#elif defined(CONFIG_SOC_SERIES_STM32G0X)
34#include <zephyr/dt-bindings/clock/stm32g0_clock.h>
35#elif defined(CONFIG_SOC_SERIES_STM32G4X)
36#include <zephyr/dt-bindings/clock/stm32g4_clock.h>
37#elif defined(CONFIG_SOC_SERIES_STM32L0X)
38#include <zephyr/dt-bindings/clock/stm32l0_clock.h>
39#elif defined(CONFIG_SOC_SERIES_STM32L1X)
40#include <zephyr/dt-bindings/clock/stm32l1_clock.h>
41#elif defined(CONFIG_SOC_SERIES_STM32L4X) || \
42 defined(CONFIG_SOC_SERIES_STM32L5X)
43#include <zephyr/dt-bindings/clock/stm32l4_clock.h>
44#elif defined(CONFIG_SOC_SERIES_STM32WBX)
45#include <zephyr/dt-bindings/clock/stm32wb_clock.h>
46#elif defined(CONFIG_SOC_SERIES_STM32WB0X)
47#include <zephyr/dt-bindings/clock/stm32wb0_clock.h>
48#elif defined(CONFIG_SOC_SERIES_STM32WLX)
49#include <zephyr/dt-bindings/clock/stm32wl_clock.h>
50#elif defined(CONFIG_SOC_SERIES_STM32H5X)
51#include <zephyr/dt-bindings/clock/stm32h5_clock.h>
52#elif defined(CONFIG_SOC_SERIES_STM32H7X)
53#include <zephyr/dt-bindings/clock/stm32h7_clock.h>
54#elif defined(CONFIG_SOC_SERIES_STM32H7RSX)
55#include <zephyr/dt-bindings/clock/stm32h7rs_clock.h>
56#elif defined(CONFIG_SOC_SERIES_STM32MP13X)
57#include <zephyr/dt-bindings/clock/stm32mp13_clock.h>
58#elif defined(CONFIG_SOC_SERIES_STM32N6X)
59#include <zephyr/dt-bindings/clock/stm32n6_clock.h>
60#elif defined(CONFIG_SOC_SERIES_STM32U0X)
61#include <zephyr/dt-bindings/clock/stm32u0_clock.h>
62#elif defined(CONFIG_SOC_SERIES_STM32U5X)
63#include <zephyr/dt-bindings/clock/stm32u5_clock.h>
64#elif defined(CONFIG_SOC_SERIES_STM32WBAX)
65#include <zephyr/dt-bindings/clock/stm32wba_clock.h>
66#else
67#include <zephyr/dt-bindings/clock/stm32_clock.h>
68#endif
69
71#define STM32_CLOCK_CONTROL_NODE DT_NODELABEL(rcc)
72
75#define STM32_AHB_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb_prescaler)
76#define STM32_APB1_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb1_prescaler)
77#define STM32_APB2_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb2_prescaler)
78#define STM32_APB3_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb3_prescaler)
79#define STM32_APB4_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb4_prescaler)
80#define STM32_APB5_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb5_prescaler)
81#define STM32_APB7_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb7_prescaler)
82#define STM32_AHB3_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb3_prescaler)
83#define STM32_AHB4_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb4_prescaler)
84#define STM32_AHB5_PRESCALER DT_PROP_OR(DT_NODELABEL(rcc), ahb5_prescaler, 1)
85#define STM32_CPU1_PRESCALER DT_PROP(DT_NODELABEL(rcc), cpu1_prescaler)
86#define STM32_CPU2_PRESCALER DT_PROP(DT_NODELABEL(rcc), cpu2_prescaler)
87
88#if DT_NODE_HAS_PROP(DT_NODELABEL(rcc), ahb_prescaler)
89#define STM32_CORE_PRESCALER STM32_AHB_PRESCALER
90#elif DT_NODE_HAS_PROP(DT_NODELABEL(rcc), cpu1_prescaler)
91#define STM32_CORE_PRESCALER STM32_CPU1_PRESCALER
92#endif
93
94#if DT_NODE_HAS_PROP(DT_NODELABEL(rcc), ahb3_prescaler)
95#define STM32_FLASH_PRESCALER STM32_AHB3_PRESCALER
96#elif DT_NODE_HAS_PROP(DT_NODELABEL(rcc), ahb4_prescaler)
97#define STM32_FLASH_PRESCALER STM32_AHB4_PRESCALER
98#else
99#define STM32_FLASH_PRESCALER STM32_CORE_PRESCALER
100#endif
101
102#define STM32_ADC_PRESCALER DT_PROP(DT_NODELABEL(rcc), adc_prescaler)
103#define STM32_ADC12_PRESCALER DT_PROP(DT_NODELABEL(rcc), adc12_prescaler)
104#define STM32_ADC34_PRESCALER DT_PROP(DT_NODELABEL(rcc), adc34_prescaler)
105
107#if defined(CONFIG_SOC_SERIES_STM32H7RSX)
108#define STM32_D1CPRE DT_PROP(DT_NODELABEL(rcc), dcpre)
109#define STM32_HPRE DT_PROP(DT_NODELABEL(rcc), hpre)
110#define STM32_PPRE1 DT_PROP(DT_NODELABEL(rcc), ppre1)
111#define STM32_PPRE2 DT_PROP(DT_NODELABEL(rcc), ppre2)
112#define STM32_PPRE4 DT_PROP(DT_NODELABEL(rcc), ppre4)
113#define STM32_PPRE5 DT_PROP(DT_NODELABEL(rcc), ppre5)
114#else
115#define STM32_D1CPRE DT_PROP(DT_NODELABEL(rcc), d1cpre)
116#define STM32_HPRE DT_PROP(DT_NODELABEL(rcc), hpre)
117#define STM32_D2PPRE1 DT_PROP(DT_NODELABEL(rcc), d2ppre1)
118#define STM32_D2PPRE2 DT_PROP(DT_NODELABEL(rcc), d2ppre2)
119#define STM32_D1PPRE DT_PROP(DT_NODELABEL(rcc), d1ppre)
120#define STM32_D3PPRE DT_PROP(DT_NODELABEL(rcc), d3ppre)
121#endif /* CONFIG_SOC_SERIES_STM32H7RSX */
122
124#define STM32_AHB5_DIV DT_PROP(DT_NODELABEL(rcc), ahb5_div)
125
126#define DT_RCC_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(rcc))
127
128/* To enable use of IS_ENABLED utility macro, these symbols
129 * should not be defined directly using DT_SAME_NODE.
130 */
131#if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(pll))
132#define STM32_SYSCLK_SRC_PLL 1
133#endif
134#if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
135#define STM32_SYSCLK_SRC_HSI 1
136#endif
137#if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
138#define STM32_SYSCLK_SRC_HSE 1
139#endif
140#if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
141#define STM32_SYSCLK_SRC_MSI 1
142#endif
143#if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_msis))
144#define STM32_SYSCLK_SRC_MSIS 1
145#endif
146#if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_csi))
147#define STM32_SYSCLK_SRC_CSI 1
148#endif
149#if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(ic2))
150#define STM32_SYSCLK_SRC_IC2 1
151#endif
152
153#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(rcc), st_stm32n6_rcc, okay)
154#if (DT_SAME_NODE(DT_CLOCKS_CTLR_BY_IDX(DT_NODELABEL(cpusw), 0), DT_NODELABEL(rcc)))
155#if (DT_CLOCKS_CELL_BY_IDX(DT_NODELABEL(cpusw), 0, bus) == STM32_SRC_HSI)
156#define STM32_CPUCLK_SRC_HSI 1
157#elif (DT_CLOCKS_CELL_BY_IDX(DT_NODELABEL(cpusw), 0, bus) == STM32_SRC_MSI)
158#define STM32_CPUCLK_SRC_MSI 1
159#elif (DT_CLOCKS_CELL_BY_IDX(DT_NODELABEL(cpusw), 0, bus) == STM32_SRC_HSE)
160#define STM32_CPUCLK_SRC_HSE 1
161#elif (DT_CLOCKS_CELL_BY_IDX(DT_NODELABEL(cpusw), 0, bus) == STM32_SRC_IC1)
162#define STM32_CPUCLK_SRC_IC1 1
163#endif
164#endif /* cpusw clk source is rcc */
165
166#define STM32_TIMG_PRESCALER DT_PROP(DT_NODELABEL(rcc), timg_prescaler)
167#endif /* rcc node compatible st_stm32n6_rcc and okay */
168
171#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f2_pll_clock, okay) || \
172 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f4_pll_clock, okay) || \
173 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f7_pll_clock, okay) || \
174 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g0_pll_clock, okay) || \
175 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g4_pll_clock, okay) || \
176 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l4_pll_clock, okay) || \
177 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32u0_pll_clock, okay) || \
178 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32u5_pll_clock, okay) || \
179 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wb_pll_clock, okay) || \
180 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wba_pll_clock, okay) || \
181 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32h7_pll_clock, okay) || \
182 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32h7rs_pll_clock, okay) || \
183 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32mp13_pll_clock, okay)
184#define STM32_PLL_ENABLED 1
185#define STM32_PLL_M_DIVISOR DT_PROP(DT_NODELABEL(pll), div_m)
186#define STM32_PLL_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul_n)
187#define STM32_PLL_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_p)
188#define STM32_PLL_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_p, 1)
189#define STM32_PLL_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_q)
190#define STM32_PLL_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_q, 1)
191#define STM32_PLL_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_r)
192#define STM32_PLL_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_r, 1)
193#define STM32_PLL_S_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_s)
194#define STM32_PLL_S_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_s, 1)
195#define STM32_PLL_FRACN_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), fracn)
196#define STM32_PLL_FRACN_VALUE DT_PROP_OR(DT_NODELABEL(pll), fracn, 1)
197#endif
198
199#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(plli2s), st_stm32f4_plli2s_clock, okay)
200#define STM32_PLLI2S_ENABLED 1
201#define STM32_PLLI2S_M_DIVISOR STM32_PLL_M_DIVISOR
202#define STM32_PLLI2S_N_MULTIPLIER DT_PROP(DT_NODELABEL(plli2s), mul_n)
203#define STM32_PLLI2S_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(plli2s), div_r)
204#define STM32_PLLI2S_R_DIVISOR DT_PROP_OR(DT_NODELABEL(plli2s), div_r, 1)
205#endif
206
207#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(plli2s), st_stm32f411_plli2s_clock, okay)
208#define STM32_PLLI2S_ENABLED 1
209#define STM32_PLLI2S_M_DIVISOR DT_PROP(DT_NODELABEL(plli2s), div_m)
210#define STM32_PLLI2S_N_MULTIPLIER DT_PROP(DT_NODELABEL(plli2s), mul_n)
211#define STM32_PLLI2S_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(plli2s), div_q)
212#define STM32_PLLI2S_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(plli2s), div_q, 1)
213#define STM32_PLLI2S_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(plli2s), div_r)
214#define STM32_PLLI2S_R_DIVISOR DT_PROP_OR(DT_NODELABEL(plli2s), div_r, 1)
215#endif
216
217#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32u5_pll_clock, okay) || \
218 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32h7_pll_clock, okay) || \
219 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32h7rs_pll_clock, okay) || \
220 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32mp13_pll_clock, okay)
221#define STM32_PLL2_ENABLED 1
222#define STM32_PLL2_M_DIVISOR DT_PROP(DT_NODELABEL(pll2), div_m)
223#define STM32_PLL2_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll2), mul_n)
224#define STM32_PLL2_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_p)
225#define STM32_PLL2_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_p, 1)
226#define STM32_PLL2_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_q)
227#define STM32_PLL2_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_q, 1)
228#define STM32_PLL2_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_r)
229#define STM32_PLL2_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_r, 1)
230#define STM32_PLL2_S_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_s)
231#define STM32_PLL2_S_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_s, 1)
232#define STM32_PLL2_T_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_t)
233#define STM32_PLL2_T_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_t, 1)
234#define STM32_PLL2_FRACN_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), fracn)
235#define STM32_PLL2_FRACN_VALUE DT_PROP_OR(DT_NODELABEL(pll2), fracn, 1)
236#endif
237
238#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32h7_pll_clock, okay) || \
239 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32u5_pll_clock, okay) || \
240 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32h7rs_pll_clock, okay) || \
241 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32mp13_pll_clock, okay)
242#define STM32_PLL3_ENABLED 1
243#define STM32_PLL3_M_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_m)
244#define STM32_PLL3_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll3), mul_n)
245#define STM32_PLL3_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_p)
246#define STM32_PLL3_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pll3), div_p, 1)
247#define STM32_PLL3_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_q)
248#define STM32_PLL3_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pll3), div_q, 1)
249#define STM32_PLL3_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_r)
250#define STM32_PLL3_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pll3), div_r, 1)
251#define STM32_PLL3_S_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_s)
252#define STM32_PLL3_S_DIVISOR DT_PROP_OR(DT_NODELABEL(pll3), div_s, 1)
253#define STM32_PLL3_FRACN_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), fracn)
254#define STM32_PLL3_FRACN_VALUE DT_PROP_OR(DT_NODELABEL(pll3), fracn, 1)
255#endif
256
257#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll4), st_stm32mp13_pll_clock, okay)
258#define STM32_PLL4_ENABLED 1
259#define STM32_PLL4_M_DIVISOR DT_PROP(DT_NODELABEL(pll4), div_m)
260#define STM32_PLL4_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll4), mul_n)
261#define STM32_PLL4_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll4), div_p)
262#define STM32_PLL4_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pll4), div_p, 1)
263#define STM32_PLL4_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll4), div_q)
264#define STM32_PLL4_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pll4), div_q, 1)
265#define STM32_PLL4_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll4), div_r)
266#define STM32_PLL4_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pll4), div_r, 1)
267#define STM32_PLL4_FRACN_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll4), fracn)
268#define STM32_PLL4_FRACN_VALUE DT_PROP_OR(DT_NODELABEL(pll4), fracn, 1)
269#endif
270
271#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f1_pll_clock, okay)
272#define STM32_PLL_ENABLED 1
273#define STM32_PLL_XTPRE DT_PROP(DT_NODELABEL(pll), xtpre)
274#define STM32_PLL_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul)
275#define STM32_PLL_USBPRE DT_PROP(DT_NODELABEL(pll), usbpre)
276#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f0_pll_clock, okay) || \
277 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f100_pll_clock, okay) || \
278 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f105_pll_clock, okay)
279#define STM32_PLL_ENABLED 1
280#define STM32_PLL_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul)
281#define STM32_PLL_PREDIV DT_PROP(DT_NODELABEL(pll), prediv)
282#define STM32_PLL_USBPRE DT_PROP(DT_NODELABEL(pll), otgfspre)
283#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l0_pll_clock, okay)
284#define STM32_PLL_ENABLED 1
285#define STM32_PLL_DIVISOR DT_PROP(DT_NODELABEL(pll), div)
286#define STM32_PLL_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul)
287#endif
288
289#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32f105_pll2_clock, okay)
290#define STM32_PLL2_ENABLED 1
291#define STM32_PLL2_MULTIPLIER DT_PROP(DT_NODELABEL(pll2), mul)
292#define STM32_PLL2_PREDIV DT_PROP(DT_NODELABEL(pll2), prediv)
293#endif
294
295#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll1), st_stm32n6_pll_clock, okay)
296#define STM32_PLL1_ENABLED 1
297#define STM32_PLL1_M_DIVISOR DT_PROP(DT_NODELABEL(pll1), div_m)
298#define STM32_PLL1_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll1), mul_n)
299#define STM32_PLL1_P1_DIVISOR DT_PROP(DT_NODELABEL(pll1), div_p1)
300#define STM32_PLL1_P2_DIVISOR DT_PROP(DT_NODELABEL(pll1), div_p2)
301#endif
302
303#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32n6_pll_clock, okay)
304#define STM32_PLL2_ENABLED 1
305#define STM32_PLL2_M_DIVISOR DT_PROP(DT_NODELABEL(pll2), div_m)
306#define STM32_PLL2_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll2), mul_n)
307#define STM32_PLL2_P1_DIVISOR DT_PROP(DT_NODELABEL(pll2), div_p1)
308#define STM32_PLL2_P2_DIVISOR DT_PROP(DT_NODELABEL(pll2), div_p2)
309#endif
310
311#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32n6_pll_clock, okay)
312#define STM32_PLL3_ENABLED 1
313#define STM32_PLL3_M_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_m)
314#define STM32_PLL3_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll3), mul_n)
315#define STM32_PLL3_P1_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_p1)
316#define STM32_PLL3_P2_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_p2)
317#endif
318
319#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll4), st_stm32n6_pll_clock, okay)
320#define STM32_PLL4_ENABLED 1
321#define STM32_PLL4_M_DIVISOR DT_PROP(DT_NODELABEL(pll4), div_m)
322#define STM32_PLL4_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll4), mul_n)
323#define STM32_PLL4_P1_DIVISOR DT_PROP(DT_NODELABEL(pll4), div_p1)
324#define STM32_PLL4_P2_DIVISOR DT_PROP(DT_NODELABEL(pll4), div_p2)
325#endif
326
328#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pll)) && \
329 DT_NODE_HAS_PROP(DT_NODELABEL(pll), clocks)
330#define DT_PLL_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll))
331#if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
332#define STM32_PLL_SRC_MSI 1
333#endif
334#if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_msis))
335#define STM32_PLL_SRC_MSIS 1
336#endif
337#if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
338#define STM32_PLL_SRC_HSI 1
339#endif
340#if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_csi))
341#define STM32_PLL_SRC_CSI 1
342#endif
343#if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
344#define STM32_PLL_SRC_HSE 1
345#endif
346#if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(pll2))
347#define STM32_PLL_SRC_PLL2 1
348#endif
349
350#endif
351
353#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pll2)) && \
354 DT_NODE_HAS_PROP(DT_NODELABEL(pll2), clocks)
355#define DT_PLL2_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll2))
356#if DT_SAME_NODE(DT_PLL2_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
357#define STM32_PLL2_SRC_MSI 1
358#endif
359#if DT_SAME_NODE(DT_PLL2_CLOCKS_CTRL, DT_NODELABEL(clk_msis))
360#define STM32_PLL2_SRC_MSIS 1
361#endif
362#if DT_SAME_NODE(DT_PLL2_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
363#define STM32_PLL2_SRC_HSI 1
364#endif
365#if DT_SAME_NODE(DT_PLL2_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
366#define STM32_PLL2_SRC_HSE 1
367#endif
368
369#endif
370
372#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pll3)) && \
373 DT_NODE_HAS_PROP(DT_NODELABEL(pll3), clocks)
374#define DT_PLL3_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll3))
375#if DT_SAME_NODE(DT_PLL3_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
376#define STM32_PLL3_SRC_MSI 1
377#endif
378#if DT_SAME_NODE(DT_PLL3_CLOCKS_CTRL, DT_NODELABEL(clk_msis))
379#define STM32_PLL3_SRC_MSIS 1
380#endif
381#if DT_SAME_NODE(DT_PLL3_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
382#define STM32_PLL3_SRC_HSI 1
383#endif
384#if DT_SAME_NODE(DT_PLL3_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
385#define STM32_PLL3_SRC_HSE 1
386#endif
387
388#endif
389
391#if DT_NODE_HAS_STATUS(DT_NODELABEL(pll4), okay) && \
392 DT_NODE_HAS_PROP(DT_NODELABEL(pll4), clocks)
393#define DT_PLL4_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll4))
394#if DT_SAME_NODE(DT_PLL4_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
395#define STM32_PLL4_SRC_MSI 1
396#endif
397#if DT_SAME_NODE(DT_PLL4_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
398#define STM32_PLL4_SRC_HSI 1
399#endif
400#if DT_SAME_NODE(DT_PLL4_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
401#define STM32_PLL4_SRC_HSE 1
402#endif
403
404#endif
405
406
409#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lse), fixed_clock, okay)
410#define STM32_LSE_ENABLED 1
411#define STM32_LSE_FREQ DT_PROP(DT_NODELABEL(clk_lse), clock_frequency)
412#define STM32_LSE_DRIVING 0
413#define STM32_LSE_BYPASS DT_PROP(DT_NODELABEL(clk_lse), lse_bypass)
414#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lse), st_stm32_lse_clock, okay)
415#define STM32_LSE_ENABLED 1
416#define STM32_LSE_FREQ DT_PROP(DT_NODELABEL(clk_lse), clock_frequency)
417#define STM32_LSE_DRIVING DT_PROP(DT_NODELABEL(clk_lse), driving_capability)
418#define STM32_LSE_BYPASS DT_PROP(DT_NODELABEL(clk_lse), lse_bypass)
419#else
420#define STM32_LSE_ENABLED 0
421#define STM32_LSE_FREQ 0
422#define STM32_LSE_DRIVING 0
423#define STM32_LSE_BYPASS 0
424#endif
425
426#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32_msi_clock, okay) || \
427 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32l0_msi_clock, okay)
428#define STM32_MSI_ENABLED 1
429#define STM32_MSI_RANGE DT_PROP(DT_NODELABEL(clk_msi), msi_range)
430#endif
431
432#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32_msi_clock, okay)
433#define STM32_MSI_ENABLED 1
434#define STM32_MSI_PLL_MODE DT_PROP(DT_NODELABEL(clk_msi), msi_pll_mode)
435#endif
436
437#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msis), st_stm32u5_msi_clock, okay)
438#define STM32_MSIS_ENABLED 1
439#define STM32_MSIS_RANGE DT_PROP(DT_NODELABEL(clk_msis), msi_range)
440#define STM32_MSIS_PLL_MODE DT_PROP(DT_NODELABEL(clk_msis), msi_pll_mode)
441#else
442#define STM32_MSIS_ENABLED 0
443#define STM32_MSIS_RANGE 0
444#define STM32_MSIS_PLL_MODE 0
445#endif
446
447#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msik), st_stm32u5_msi_clock, okay)
448#define STM32_MSIK_ENABLED 1
449#define STM32_MSIK_RANGE DT_PROP(DT_NODELABEL(clk_msik), msi_range)
450#define STM32_MSIK_PLL_MODE DT_PROP(DT_NODELABEL(clk_msik), msi_pll_mode)
451#else
452#define STM32_MSIK_ENABLED 0
453#define STM32_MSIK_RANGE 0
454#define STM32_MSIK_PLL_MODE 0
455#endif
456
457#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_csi), fixed_clock, okay)
458#define STM32_CSI_ENABLED 1
459#define STM32_CSI_FREQ DT_PROP(DT_NODELABEL(clk_csi), clock_frequency)
460#else
461#define STM32_CSI_FREQ 0
462#endif
463
464#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lsi), fixed_clock, okay)
465#define STM32_LSI_ENABLED 1
466#define STM32_LSI_FREQ DT_PROP(DT_NODELABEL(clk_lsi), clock_frequency)
467#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lsi1), fixed_clock, okay)
468#define STM32_LSI_ENABLED 1
469#define STM32_LSI_FREQ DT_PROP(DT_NODELABEL(clk_lsi1), clock_frequency)
470#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lsi2), fixed_clock, okay)
471#define STM32_LSI_ENABLED 1
472#define STM32_LSI_FREQ DT_PROP(DT_NODELABEL(clk_lsi2), clock_frequency)
473#else
474#define STM32_LSI_FREQ 0
475#endif
476
477#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), fixed_clock, okay)
478#define STM32_HSI_DIV_ENABLED 0
479#define STM32_HSI_ENABLED 1
480#define STM32_HSI_FREQ DT_PROP(DT_NODELABEL(clk_hsi), clock_frequency)
481#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32h7_hsi_clock, okay) \
482 || DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32g0_hsi_clock, okay) \
483 || DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32c0_hsi_clock, okay) \
484 || DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32n6_hsi_clock, okay)
485#define STM32_HSI_DIV_ENABLED 1
486#define STM32_HSI_ENABLED 1
487#define STM32_HSI_DIVISOR DT_PROP(DT_NODELABEL(clk_hsi), hsi_div)
488#define STM32_HSI_FREQ DT_PROP(DT_NODELABEL(clk_hsi), clock_frequency)
489#else
490#define STM32_HSI_DIV_ENABLED 0
491#define STM32_HSI_DIVISOR 1
492#define STM32_HSI_FREQ 0
493#endif
494
495#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), fixed_clock, okay)
496#define STM32_HSE_ENABLED 1
497#define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency)
498#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32_hse_clock, okay)
499#define STM32_HSE_ENABLED 1
500#define STM32_HSE_BYPASS DT_PROP(DT_NODELABEL(clk_hse), hse_bypass)
501#define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency)
502#define STM32_HSE_CSS DT_PROP(DT_NODELABEL(clk_hse), css_enabled)
503#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32wl_hse_clock, okay)
504#define STM32_HSE_ENABLED 1
505#define STM32_HSE_TCXO DT_PROP(DT_NODELABEL(clk_hse), hse_tcxo)
506#define STM32_HSE_DIV2 DT_PROP(DT_NODELABEL(clk_hse), hse_div2)
507#define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency)
508#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32wba_hse_clock, okay)
509#define STM32_HSE_ENABLED 1
510#define STM32_HSE_DIV2 DT_PROP(DT_NODELABEL(clk_hse), hse_div2)
511#define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency)
512#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32n6_hse_clock, okay)
513#define STM32_HSE_ENABLED 1
514#define STM32_HSE_BYPASS DT_PROP(DT_NODELABEL(clk_hse), hse_bypass)
515#define STM32_HSE_DIV2 DT_PROP(DT_NODELABEL(clk_hse), hse_div2)
516#define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency)
517#else
518#define STM32_HSE_FREQ 0
519#endif
520
521#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi48), fixed_clock, okay)
522#define STM32_HSI48_ENABLED 1
523#define STM32_HSI48_FREQ DT_PROP(DT_NODELABEL(clk_hsi48), clock_frequency)
524#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi48), st_stm32_hsi48_clock, okay)
525#define STM32_HSI48_ENABLED 1
526#define STM32_HSI48_FREQ DT_PROP(DT_NODELABEL(clk_hsi48), clock_frequency)
527#define STM32_HSI48_CRS_USB_SOF DT_PROP(DT_NODELABEL(clk_hsi48), crs_usb_sof)
528#endif
529
530#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(perck), st_stm32_clock_mux, okay)
531#define STM32_CKPER_ENABLED 1
532#endif
533
534#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(cpusw), st_stm32_clock_mux, okay)
535#define STM32_CPUSW_ENABLED 1
536#endif
537
538#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic1), st_stm32n6_ic_clock_mux, okay)
539#define STM32_IC1_ENABLED 1
540#define STM32_IC1_PLL_SRC DT_PROP(DT_NODELABEL(ic1), pll_src)
541#define STM32_IC1_DIV DT_PROP(DT_NODELABEL(ic1), ic_div)
542#endif
543
544#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic2), st_stm32n6_ic_clock_mux, okay)
545#define STM32_IC2_ENABLED 1
546#define STM32_IC2_PLL_SRC DT_PROP(DT_NODELABEL(ic2), pll_src)
547#define STM32_IC2_DIV DT_PROP(DT_NODELABEL(ic2), ic_div)
548#endif
549
550#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic3), st_stm32n6_ic_clock_mux, okay)
551#define STM32_IC3_ENABLED 1
552#define STM32_IC3_PLL_SRC DT_PROP(DT_NODELABEL(ic3), pll_src)
553#define STM32_IC3_DIV DT_PROP(DT_NODELABEL(ic3), ic_div)
554#endif
555
556#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic4), st_stm32n6_ic_clock_mux, okay)
557#define STM32_IC4_ENABLED 1
558#define STM32_IC4_PLL_SRC DT_PROP(DT_NODELABEL(ic4), pll_src)
559#define STM32_IC4_DIV DT_PROP(DT_NODELABEL(ic4), ic_div)
560#endif
561
562#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic5), st_stm32n6_ic_clock_mux, okay)
563#define STM32_IC5_ENABLED 1
564#define STM32_IC5_PLL_SRC DT_PROP(DT_NODELABEL(ic5), pll_src)
565#define STM32_IC5_DIV DT_PROP(DT_NODELABEL(ic5), ic_div)
566#endif
567
568#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic6), st_stm32n6_ic_clock_mux, okay)
569#define STM32_IC6_ENABLED 1
570#define STM32_IC6_PLL_SRC DT_PROP(DT_NODELABEL(ic6), pll_src)
571#define STM32_IC6_DIV DT_PROP(DT_NODELABEL(ic6), ic_div)
572#endif
573
574#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic7), st_stm32n6_ic_clock_mux, okay)
575#define STM32_IC7_ENABLED 1
576#define STM32_IC7_PLL_SRC DT_PROP(DT_NODELABEL(ic7), pll_src)
577#define STM32_IC7_DIV DT_PROP(DT_NODELABEL(ic7), ic_div)
578#endif
579
580#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic8), st_stm32n6_ic_clock_mux, okay)
581#define STM32_IC8_ENABLED 1
582#define STM32_IC8_PLL_SRC DT_PROP(DT_NODELABEL(ic8), pll_src)
583#define STM32_IC8_DIV DT_PROP(DT_NODELABEL(ic8), ic_div)
584#endif
585
586#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic9), st_stm32n6_ic_clock_mux, okay)
587#define STM32_IC9_ENABLED 1
588#define STM32_IC9_PLL_SRC DT_PROP(DT_NODELABEL(ic9), pll_src)
589#define STM32_IC9_DIV DT_PROP(DT_NODELABEL(ic9), ic_div)
590#endif
591
592#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic10), st_stm32n6_ic_clock_mux, okay)
593#define STM32_IC10_ENABLED 1
594#define STM32_IC10_PLL_SRC DT_PROP(DT_NODELABEL(ic10), pll_src)
595#define STM32_IC10_DIV DT_PROP(DT_NODELABEL(ic10), ic_div)
596#endif
597
598#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic11), st_stm32n6_ic_clock_mux, okay)
599#define STM32_IC11_ENABLED 1
600#define STM32_IC11_PLL_SRC DT_PROP(DT_NODELABEL(ic11), pll_src)
601#define STM32_IC11_DIV DT_PROP(DT_NODELABEL(ic11), ic_div)
602#endif
603
604#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic12), st_stm32n6_ic_clock_mux, okay)
605#define STM32_IC12_ENABLED 1
606#define STM32_IC12_PLL_SRC DT_PROP(DT_NODELABEL(ic12), pll_src)
607#define STM32_IC12_DIV DT_PROP(DT_NODELABEL(ic12), ic_div)
608#endif
609
610#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic13), st_stm32n6_ic_clock_mux, okay)
611#define STM32_IC13_ENABLED 1
612#define STM32_IC13_PLL_SRC DT_PROP(DT_NODELABEL(ic13), pll_src)
613#define STM32_IC13_DIV DT_PROP(DT_NODELABEL(ic13), ic_div)
614#endif
615
616#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic14), st_stm32n6_ic_clock_mux, okay)
617#define STM32_IC14_ENABLED 1
618#define STM32_IC14_PLL_SRC DT_PROP(DT_NODELABEL(ic14), pll_src)
619#define STM32_IC14_DIV DT_PROP(DT_NODELABEL(ic14), ic_div)
620#endif
621
622#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic15), st_stm32n6_ic_clock_mux, okay)
623#define STM32_IC15_ENABLED 1
624#define STM32_IC15_PLL_SRC DT_PROP(DT_NODELABEL(ic15), pll_src)
625#define STM32_IC15_DIV DT_PROP(DT_NODELABEL(ic15), ic_div)
626#endif
627
628#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic16), st_stm32n6_ic_clock_mux, okay)
629#define STM32_IC16_ENABLED 1
630#define STM32_IC16_PLL_SRC DT_PROP(DT_NODELABEL(ic16), pll_src)
631#define STM32_IC16_DIV DT_PROP(DT_NODELABEL(ic16), ic_div)
632#endif
633
634#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic17), st_stm32n6_ic_clock_mux, okay)
635#define STM32_IC17_ENABLED 1
636#define STM32_IC17_PLL_SRC DT_PROP(DT_NODELABEL(ic17), pll_src)
637#define STM32_IC17_DIV DT_PROP(DT_NODELABEL(ic17), ic_div)
638#endif
639
640#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic18), st_stm32n6_ic_clock_mux, okay)
641#define STM32_IC18_ENABLED 1
642#define STM32_IC18_PLL_SRC DT_PROP(DT_NODELABEL(ic18), pll_src)
643#define STM32_IC18_DIV DT_PROP(DT_NODELABEL(ic18), ic_div)
644#endif
645
646#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic19), st_stm32n6_ic_clock_mux, okay)
647#define STM32_IC19_ENABLED 1
648#define STM32_IC19_PLL_SRC DT_PROP(DT_NODELABEL(ic19), pll_src)
649#define STM32_IC19_DIV DT_PROP(DT_NODELABEL(ic19), ic_div)
650#endif
651
652#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic20), st_stm32n6_ic_clock_mux, okay)
653#define STM32_IC20_ENABLED 1
654#define STM32_IC20_PLL_SRC DT_PROP(DT_NODELABEL(ic20), pll_src)
655#define STM32_IC20_DIV DT_PROP(DT_NODELABEL(ic20), ic_div)
656#endif
657
665
668#define STM32_CLOCK_INFO(clk_index, node_id) \
669 { \
670 .enr = DT_CLOCKS_CELL_BY_IDX(node_id, clk_index, bits), \
671 .bus = DT_CLOCKS_CELL_BY_IDX(node_id, clk_index, bus) & \
672 GENMASK(STM32_CLOCK_DIV_SHIFT - 1, 0), \
673 .div = DT_CLOCKS_CELL_BY_IDX(node_id, clk_index, bus) >> \
674 STM32_CLOCK_DIV_SHIFT, \
675 }
676#define STM32_DT_CLOCKS(node_id) \
677 { \
678 LISTIFY(DT_NUM_CLOCKS(node_id), \
679 STM32_CLOCK_INFO, (,), node_id) \
680 }
681
682#define STM32_DT_INST_CLOCKS(inst) \
683 STM32_DT_CLOCKS(DT_DRV_INST(inst))
684
685#define STM32_DOMAIN_CLOCK_INST_SUPPORT(inst) DT_INST_CLOCKS_HAS_IDX(inst, 1) ||
686#define STM32_DT_INST_DEV_DOMAIN_CLOCK_SUPPORT \
687 (DT_INST_FOREACH_STATUS_OKAY(STM32_DOMAIN_CLOCK_INST_SUPPORT) 0)
688
689#define STM32_DOMAIN_CLOCK_SUPPORT(id) DT_CLOCKS_HAS_IDX(DT_NODELABEL(id), 1) ||
690#define STM32_DT_DEV_DOMAIN_CLOCK_SUPPORT \
691 (DT_FOREACH_STATUS_OKAY(STM32_DOMAIN_CLOCK_SUPPORT) 0)
692
700#define STM32_DT_CLKSEL_REG_GET(clock) \
701 (((clock) >> STM32_DT_CLKSEL_REG_SHIFT) & STM32_DT_CLKSEL_REG_MASK)
702
708#define STM32_DT_CLKSEL_SHIFT_GET(clock) \
709 (((clock) >> STM32_DT_CLKSEL_SHIFT_SHIFT) & STM32_DT_CLKSEL_SHIFT_MASK)
710
716#define STM32_DT_CLKSEL_MASK_GET(clock) \
717 (((clock) >> STM32_DT_CLKSEL_MASK_SHIFT) & STM32_DT_CLKSEL_MASK_MASK)
718
724#define STM32_DT_CLKSEL_VAL_GET(clock) \
725 (((clock) >> STM32_DT_CLKSEL_VAL_SHIFT) & STM32_DT_CLKSEL_VAL_MASK)
726
727#if defined(STM32_HSE_CSS)
736void stm32_hse_css_callback(void);
737#endif
738
739#ifdef CONFIG_SOC_SERIES_STM32WB0X
744typedef void (*lsi_update_cb_t)(uint32_t new_lsi_frequency);
745
757int stm32wb0_register_lsi_update_callback(lsi_update_cb_t cb);
758#endif /* CONFIG_SOC_SERIES_STM32WB0X */
759
760#endif /* ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_STM32_CLOCK_CONTROL_H_ */
clock_control.h
Public Clock Control APIs.
uint32_t
__UINT32_TYPE__ uint32_t
Definition stdint.h:90
stm32_clock.h
STM32_CLOCK_DIV_SHIFT
#define STM32_CLOCK_DIV_SHIFT
Definition stm32_clock.h:27
stm32c0_clock.h
stm32f0_clock.h
stm32f10x_clock.h
stm32f1_clock.h
stm32f3_clock.h
stm32f410_clock.h
stm32f4_clock.h
stm32f7_clock.h
stm32g0_clock.h
stm32g4_clock.h
stm32h5_clock.h
stm32h7_clock.h
stm32h7rs_clock.h
stm32l0_clock.h
stm32l1_clock.h
stm32l4_clock.h
stm32mp13_clock.h
stm32n6_clock.h
stm32u0_clock.h
stm32u5_clock.h
stm32wb0_clock.h
stm32wb_clock.h
stm32wba_clock.h
stm32wl_clock.h
stm32_pclken
Driver structure definition.
Definition stm32_clock_control.h:660
stm32_pclken::div
uint32_t div
Definition stm32_clock_control.h:662
stm32_pclken::bus
uint32_t bus
Definition stm32_clock_control.h:661
stm32_pclken::enr
uint32_t enr
Definition stm32_clock_control.h:663