Zephyr API Documentation 3.7.99
A Scalable Open Source RTOS
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stm32_clock_control.h
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1/*
2 * Copyright (c) 2016 Open-RnD Sp. z o.o.
3 * Copyright (c) 2016 BayLibre, SAS
4 * Copyright (c) 2017-2022 Linaro Limited.
5 * Copyright (c) 2017 RnDity Sp. z o.o.
6 * Copyright (c) 2023 STMicroelectronics
7 *
8 * SPDX-License-Identifier: Apache-2.0
9 */
10#ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_STM32_CLOCK_CONTROL_H_
11#define ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_STM32_CLOCK_CONTROL_H_
12
14
15#if defined(CONFIG_SOC_SERIES_STM32C0X)
17#elif defined(CONFIG_SOC_SERIES_STM32F0X)
19#elif defined(CONFIG_SOC_SERIES_STM32F1X)
20#if defined(CONFIG_SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE)
22#else
24#endif
25#elif defined(CONFIG_SOC_SERIES_STM32F3X)
27#elif defined(CONFIG_SOC_SERIES_STM32F2X) || \
28 defined(CONFIG_SOC_SERIES_STM32F4X)
30#elif defined(CONFIG_SOC_SERIES_STM32F7X)
32#elif defined(CONFIG_SOC_SERIES_STM32G0X)
34#elif defined(CONFIG_SOC_SERIES_STM32G4X)
36#elif defined(CONFIG_SOC_SERIES_STM32L0X)
38#elif defined(CONFIG_SOC_SERIES_STM32L1X)
40#elif defined(CONFIG_SOC_SERIES_STM32L4X) || \
41 defined(CONFIG_SOC_SERIES_STM32L5X)
43#elif defined(CONFIG_SOC_SERIES_STM32WBX)
45#elif defined(CONFIG_SOC_SERIES_STM32WB0X)
47#elif defined(CONFIG_SOC_SERIES_STM32WLX)
49#elif defined(CONFIG_SOC_SERIES_STM32H5X)
51#elif defined(CONFIG_SOC_SERIES_STM32H7X)
53#elif defined(CONFIG_SOC_SERIES_STM32H7RSX)
55#elif defined(CONFIG_SOC_SERIES_STM32U0X)
57#elif defined(CONFIG_SOC_SERIES_STM32U5X)
59#elif defined(CONFIG_SOC_SERIES_STM32WBAX)
61#else
63#endif
64
66#define STM32_CLOCK_CONTROL_NODE DT_NODELABEL(rcc)
67
70#define STM32_AHB_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb_prescaler)
71#define STM32_APB1_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb1_prescaler)
72#define STM32_APB2_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb2_prescaler)
73#define STM32_APB3_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb3_prescaler)
74#define STM32_APB5_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb5_prescaler)
75#define STM32_APB7_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb7_prescaler)
76#define STM32_AHB3_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb3_prescaler)
77#define STM32_AHB4_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb4_prescaler)
78#define STM32_AHB5_PRESCALER DT_PROP_OR(DT_NODELABEL(rcc), ahb5_prescaler, 1)
79#define STM32_CPU1_PRESCALER DT_PROP(DT_NODELABEL(rcc), cpu1_prescaler)
80#define STM32_CPU2_PRESCALER DT_PROP(DT_NODELABEL(rcc), cpu2_prescaler)
81
82#if DT_NODE_HAS_PROP(DT_NODELABEL(rcc), ahb_prescaler)
83#define STM32_CORE_PRESCALER STM32_AHB_PRESCALER
84#elif DT_NODE_HAS_PROP(DT_NODELABEL(rcc), cpu1_prescaler)
85#define STM32_CORE_PRESCALER STM32_CPU1_PRESCALER
86#endif
87
88#if DT_NODE_HAS_PROP(DT_NODELABEL(rcc), ahb3_prescaler)
89#define STM32_FLASH_PRESCALER STM32_AHB3_PRESCALER
90#elif DT_NODE_HAS_PROP(DT_NODELABEL(rcc), ahb4_prescaler)
91#define STM32_FLASH_PRESCALER STM32_AHB4_PRESCALER
92#else
93#define STM32_FLASH_PRESCALER STM32_CORE_PRESCALER
94#endif
95
96#define STM32_ADC_PRESCALER DT_PROP(DT_NODELABEL(rcc), adc_prescaler)
97#define STM32_ADC12_PRESCALER DT_PROP(DT_NODELABEL(rcc), adc12_prescaler)
98#define STM32_ADC34_PRESCALER DT_PROP(DT_NODELABEL(rcc), adc34_prescaler)
99
101#if defined(CONFIG_SOC_SERIES_STM32H7RSX)
102#define STM32_D1CPRE DT_PROP(DT_NODELABEL(rcc), dcpre)
103#define STM32_HPRE DT_PROP(DT_NODELABEL(rcc), hpre)
104#define STM32_PPRE1 DT_PROP(DT_NODELABEL(rcc), ppre1)
105#define STM32_PPRE2 DT_PROP(DT_NODELABEL(rcc), ppre2)
106#define STM32_PPRE4 DT_PROP(DT_NODELABEL(rcc), ppre4)
107#define STM32_PPRE5 DT_PROP(DT_NODELABEL(rcc), ppre5)
108#else
109#define STM32_D1CPRE DT_PROP(DT_NODELABEL(rcc), d1cpre)
110#define STM32_HPRE DT_PROP(DT_NODELABEL(rcc), hpre)
111#define STM32_D2PPRE1 DT_PROP(DT_NODELABEL(rcc), d2ppre1)
112#define STM32_D2PPRE2 DT_PROP(DT_NODELABEL(rcc), d2ppre2)
113#define STM32_D1PPRE DT_PROP(DT_NODELABEL(rcc), d1ppre)
114#define STM32_D3PPRE DT_PROP(DT_NODELABEL(rcc), d3ppre)
115#endif /* CONFIG_SOC_SERIES_STM32H7RSX */
116
118#define STM32_AHB5_DIV DT_PROP(DT_NODELABEL(rcc), ahb5_div)
119
120#define DT_RCC_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(rcc))
121
122/* To enable use of IS_ENABLED utility macro, these symbols
123 * should not be defined directly using DT_SAME_NODE.
124 */
125#if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(pll))
126#define STM32_SYSCLK_SRC_PLL 1
127#endif
128#if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
129#define STM32_SYSCLK_SRC_HSI 1
130#endif
131#if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
132#define STM32_SYSCLK_SRC_HSE 1
133#endif
134#if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
135#define STM32_SYSCLK_SRC_MSI 1
136#endif
137#if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_msis))
138#define STM32_SYSCLK_SRC_MSIS 1
139#endif
140#if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_csi))
141#define STM32_SYSCLK_SRC_CSI 1
142#endif
143
144
147#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f2_pll_clock, okay) || \
148 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f4_pll_clock, okay) || \
149 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f7_pll_clock, okay) || \
150 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g0_pll_clock, okay) || \
151 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g4_pll_clock, okay) || \
152 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l4_pll_clock, okay) || \
153 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32u0_pll_clock, okay) || \
154 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32u5_pll_clock, okay) || \
155 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wb_pll_clock, okay) || \
156 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wba_pll_clock, okay) || \
157 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32h7_pll_clock, okay) || \
158 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32h7rs_pll_clock, okay)
159#define STM32_PLL_ENABLED 1
160#define STM32_PLL_M_DIVISOR DT_PROP(DT_NODELABEL(pll), div_m)
161#define STM32_PLL_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul_n)
162#define STM32_PLL_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_p)
163#define STM32_PLL_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_p, 1)
164#define STM32_PLL_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_q)
165#define STM32_PLL_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_q, 1)
166#define STM32_PLL_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_r)
167#define STM32_PLL_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_r, 1)
168#define STM32_PLL_S_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_s)
169#define STM32_PLL_S_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_s, 1)
170#define STM32_PLL_FRACN_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), fracn)
171#define STM32_PLL_FRACN_VALUE DT_PROP_OR(DT_NODELABEL(pll), fracn, 1)
172#endif
173
174#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(plli2s), st_stm32f4_plli2s_clock, okay)
175#define STM32_PLLI2S_ENABLED 1
176#define STM32_PLLI2S_M_DIVISOR STM32_PLL_M_DIVISOR
177#define STM32_PLLI2S_N_MULTIPLIER DT_PROP(DT_NODELABEL(plli2s), mul_n)
178#define STM32_PLLI2S_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(plli2s), div_r)
179#define STM32_PLLI2S_R_DIVISOR DT_PROP_OR(DT_NODELABEL(plli2s), div_r, 1)
180#endif
181
182#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(plli2s), st_stm32f412_plli2s_clock, okay)
183#define STM32_PLLI2S_ENABLED 1
184#define STM32_PLLI2S_M_DIVISOR DT_PROP(DT_NODELABEL(plli2s), div_m)
185#define STM32_PLLI2S_N_MULTIPLIER DT_PROP(DT_NODELABEL(plli2s), mul_n)
186#define STM32_PLLI2S_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(plli2s), div_r)
187#define STM32_PLLI2S_R_DIVISOR DT_PROP_OR(DT_NODELABEL(plli2s), div_r, 1)
188#endif
189
190#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32u5_pll_clock, okay) || \
191 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32h7_pll_clock, okay) || \
192 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32h7rs_pll_clock, okay)
193#define STM32_PLL2_ENABLED 1
194#define STM32_PLL2_M_DIVISOR DT_PROP(DT_NODELABEL(pll2), div_m)
195#define STM32_PLL2_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll2), mul_n)
196#define STM32_PLL2_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_p)
197#define STM32_PLL2_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_p, 1)
198#define STM32_PLL2_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_q)
199#define STM32_PLL2_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_q, 1)
200#define STM32_PLL2_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_r)
201#define STM32_PLL2_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_r, 1)
202#define STM32_PLL2_S_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_s)
203#define STM32_PLL2_S_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_s, 1)
204#define STM32_PLL2_T_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_t)
205#define STM32_PLL2_T_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_t, 1)
206#define STM32_PLL2_FRACN_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), fracn)
207#define STM32_PLL2_FRACN_VALUE DT_PROP_OR(DT_NODELABEL(pll2), fracn, 1)
208#endif
209
210#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32h7_pll_clock, okay) || \
211 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32u5_pll_clock, okay) || \
212 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32h7rs_pll_clock, okay)
213#define STM32_PLL3_ENABLED 1
214#define STM32_PLL3_M_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_m)
215#define STM32_PLL3_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll3), mul_n)
216#define STM32_PLL3_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_p)
217#define STM32_PLL3_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pll3), div_p, 1)
218#define STM32_PLL3_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_q)
219#define STM32_PLL3_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pll3), div_q, 1)
220#define STM32_PLL3_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_r)
221#define STM32_PLL3_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pll3), div_r, 1)
222#define STM32_PLL3_S_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_s)
223#define STM32_PLL3_S_DIVISOR DT_PROP_OR(DT_NODELABEL(pll3), div_s, 1)
224#define STM32_PLL3_FRACN_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), fracn)
225#define STM32_PLL3_FRACN_VALUE DT_PROP_OR(DT_NODELABEL(pll3), fracn, 1)
226#endif
227
228#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f1_pll_clock, okay)
229#define STM32_PLL_ENABLED 1
230#define STM32_PLL_XTPRE DT_PROP(DT_NODELABEL(pll), xtpre)
231#define STM32_PLL_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul)
232#define STM32_PLL_USBPRE DT_PROP(DT_NODELABEL(pll), usbpre)
233#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f0_pll_clock, okay) || \
234 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f100_pll_clock, okay) || \
235 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f105_pll_clock, okay)
236#define STM32_PLL_ENABLED 1
237#define STM32_PLL_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul)
238#define STM32_PLL_PREDIV DT_PROP(DT_NODELABEL(pll), prediv)
239#define STM32_PLL_USBPRE DT_PROP(DT_NODELABEL(pll), otgfspre)
240#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l0_pll_clock, okay)
241#define STM32_PLL_ENABLED 1
242#define STM32_PLL_DIVISOR DT_PROP(DT_NODELABEL(pll), div)
243#define STM32_PLL_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul)
244#endif
245
246#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32f105_pll2_clock, okay)
247#define STM32_PLL2_ENABLED 1
248#define STM32_PLL2_MULTIPLIER DT_PROP(DT_NODELABEL(pll2), mul)
249#define STM32_PLL2_PREDIV DT_PROP(DT_NODELABEL(pll2), prediv)
250#endif
251
253#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pll)) && \
254 DT_NODE_HAS_PROP(DT_NODELABEL(pll), clocks)
255#define DT_PLL_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll))
256#if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
257#define STM32_PLL_SRC_MSI 1
258#endif
259#if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_msis))
260#define STM32_PLL_SRC_MSIS 1
261#endif
262#if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
263#define STM32_PLL_SRC_HSI 1
264#endif
265#if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_csi))
266#define STM32_PLL_SRC_CSI 1
267#endif
268#if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
269#define STM32_PLL_SRC_HSE 1
270#endif
271#if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(pll2))
272#define STM32_PLL_SRC_PLL2 1
273#endif
274
275#endif
276
278#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pll2)) && \
279 DT_NODE_HAS_PROP(DT_NODELABEL(pll2), clocks)
280#define DT_PLL2_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll2))
281#if DT_SAME_NODE(DT_PLL2_CLOCKS_CTRL, DT_NODELABEL(clk_msis))
282#define STM32_PLL2_SRC_MSIS 1
283#endif
284#if DT_SAME_NODE(DT_PLL2_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
285#define STM32_PLL2_SRC_HSI 1
286#endif
287#if DT_SAME_NODE(DT_PLL2_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
288#define STM32_PLL2_SRC_HSE 1
289#endif
290
291#endif
292
294#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pll3)) && \
295 DT_NODE_HAS_PROP(DT_NODELABEL(pll3), clocks)
296#define DT_PLL3_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll3))
297#if DT_SAME_NODE(DT_PLL3_CLOCKS_CTRL, DT_NODELABEL(clk_msis))
298#define STM32_PLL3_SRC_MSIS 1
299#endif
300#if DT_SAME_NODE(DT_PLL3_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
301#define STM32_PLL3_SRC_HSI 1
302#endif
303#if DT_SAME_NODE(DT_PLL3_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
304#define STM32_PLL3_SRC_HSE 1
305#endif
306
307#endif
308
309
312#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lse), fixed_clock, okay)
313#define STM32_LSE_ENABLED 1
314#define STM32_LSE_FREQ DT_PROP(DT_NODELABEL(clk_lse), clock_frequency)
315#define STM32_LSE_DRIVING 0
316#define STM32_LSE_BYPASS DT_PROP(DT_NODELABEL(clk_lse), lse_bypass)
317#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lse), st_stm32_lse_clock, okay)
318#define STM32_LSE_ENABLED 1
319#define STM32_LSE_FREQ DT_PROP(DT_NODELABEL(clk_lse), clock_frequency)
320#define STM32_LSE_DRIVING DT_PROP(DT_NODELABEL(clk_lse), driving_capability)
321#define STM32_LSE_BYPASS DT_PROP(DT_NODELABEL(clk_lse), lse_bypass)
322#else
323#define STM32_LSE_ENABLED 0
324#define STM32_LSE_FREQ 0
325#define STM32_LSE_DRIVING 0
326#define STM32_LSE_BYPASS 0
327#endif
328
329#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32_msi_clock, okay) || \
330 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32l0_msi_clock, okay)
331#define STM32_MSI_ENABLED 1
332#define STM32_MSI_RANGE DT_PROP(DT_NODELABEL(clk_msi), msi_range)
333#endif
334
335#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32_msi_clock, okay)
336#define STM32_MSI_ENABLED 1
337#define STM32_MSI_PLL_MODE DT_PROP(DT_NODELABEL(clk_msi), msi_pll_mode)
338#endif
339
340#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msis), st_stm32u5_msi_clock, okay)
341#define STM32_MSIS_ENABLED 1
342#define STM32_MSIS_RANGE DT_PROP(DT_NODELABEL(clk_msis), msi_range)
343#define STM32_MSIS_PLL_MODE DT_PROP(DT_NODELABEL(clk_msis), msi_pll_mode)
344#else
345#define STM32_MSIS_ENABLED 0
346#define STM32_MSIS_RANGE 0
347#define STM32_MSIS_PLL_MODE 0
348#endif
349
350#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msik), st_stm32u5_msi_clock, okay)
351#define STM32_MSIK_ENABLED 1
352#define STM32_MSIK_RANGE DT_PROP(DT_NODELABEL(clk_msik), msi_range)
353#define STM32_MSIK_PLL_MODE DT_PROP(DT_NODELABEL(clk_msik), msi_pll_mode)
354#else
355#define STM32_MSIK_ENABLED 0
356#define STM32_MSIK_RANGE 0
357#define STM32_MSIK_PLL_MODE 0
358#endif
359
360#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_csi), fixed_clock, okay)
361#define STM32_CSI_ENABLED 1
362#define STM32_CSI_FREQ DT_PROP(DT_NODELABEL(clk_csi), clock_frequency)
363#else
364#define STM32_CSI_FREQ 0
365#endif
366
367#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lsi), fixed_clock, okay)
368#define STM32_LSI_ENABLED 1
369#define STM32_LSI_FREQ DT_PROP(DT_NODELABEL(clk_lsi), clock_frequency)
370#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lsi1), fixed_clock, okay)
371#define STM32_LSI_ENABLED 1
372#define STM32_LSI_FREQ DT_PROP(DT_NODELABEL(clk_lsi1), clock_frequency)
373#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lsi2), fixed_clock, okay)
374#define STM32_LSI_ENABLED 1
375#define STM32_LSI_FREQ DT_PROP(DT_NODELABEL(clk_lsi2), clock_frequency)
376#else
377#define STM32_LSI_FREQ 0
378#endif
379
380#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), fixed_clock, okay)
381#define STM32_HSI_DIV_ENABLED 0
382#define STM32_HSI_ENABLED 1
383#define STM32_HSI_FREQ DT_PROP(DT_NODELABEL(clk_hsi), clock_frequency)
384#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32h7_hsi_clock, okay) \
385 || DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32g0_hsi_clock, okay) \
386 || DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32c0_hsi_clock, okay)
387#define STM32_HSI_DIV_ENABLED 1
388#define STM32_HSI_ENABLED 1
389#define STM32_HSI_DIVISOR DT_PROP(DT_NODELABEL(clk_hsi), hsi_div)
390#define STM32_HSI_FREQ DT_PROP(DT_NODELABEL(clk_hsi), clock_frequency)
391#else
392#define STM32_HSI_DIV_ENABLED 0
393#define STM32_HSI_DIVISOR 1
394#define STM32_HSI_FREQ 0
395#endif
396
397#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), fixed_clock, okay)
398#define STM32_HSE_ENABLED 1
399#define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency)
400#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32_hse_clock, okay)
401#define STM32_HSE_ENABLED 1
402#define STM32_HSE_BYPASS DT_PROP(DT_NODELABEL(clk_hse), hse_bypass)
403#define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency)
404#define STM32_HSE_CSS DT_PROP(DT_NODELABEL(clk_hse), css_enabled)
405#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32wl_hse_clock, okay)
406#define STM32_HSE_ENABLED 1
407#define STM32_HSE_TCXO DT_PROP(DT_NODELABEL(clk_hse), hse_tcxo)
408#define STM32_HSE_DIV2 DT_PROP(DT_NODELABEL(clk_hse), hse_div2)
409#define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency)
410#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32wba_hse_clock, okay)
411#define STM32_HSE_ENABLED 1
412#define STM32_HSE_DIV2 DT_PROP(DT_NODELABEL(clk_hse), hse_div2)
413#define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency)
414#else
415#define STM32_HSE_FREQ 0
416#endif
417
418#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi48), fixed_clock, okay)
419#define STM32_HSI48_ENABLED 1
420#define STM32_HSI48_FREQ DT_PROP(DT_NODELABEL(clk_hsi48), clock_frequency)
421#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi48), st_stm32_hsi48_clock, okay)
422#define STM32_HSI48_ENABLED 1
423#define STM32_HSI48_FREQ DT_PROP(DT_NODELABEL(clk_hsi48), clock_frequency)
424#define STM32_HSI48_CRS_USB_SOF DT_PROP(DT_NODELABEL(clk_hsi48), crs_usb_sof)
425#endif
426
427#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(perck), st_stm32_clock_mux, okay)
428#define STM32_CKPER_ENABLED 1
429#endif
430
437
440#define STM32_CLOCK_INFO(clk_index, node_id) \
441 { \
442 .enr = DT_CLOCKS_CELL_BY_IDX(node_id, clk_index, bits), \
443 .bus = DT_CLOCKS_CELL_BY_IDX(node_id, clk_index, bus) \
444 }
445#define STM32_DT_CLOCKS(node_id) \
446 { \
447 LISTIFY(DT_NUM_CLOCKS(node_id), \
448 STM32_CLOCK_INFO, (,), node_id) \
449 }
450
451#define STM32_DT_INST_CLOCKS(inst) \
452 STM32_DT_CLOCKS(DT_DRV_INST(inst))
453
454#define STM32_DOMAIN_CLOCK_INST_SUPPORT(inst) DT_INST_CLOCKS_HAS_IDX(inst, 1) ||
455#define STM32_DT_INST_DEV_DOMAIN_CLOCK_SUPPORT \
456 (DT_INST_FOREACH_STATUS_OKAY(STM32_DOMAIN_CLOCK_INST_SUPPORT) 0)
457
458#define STM32_DOMAIN_CLOCK_SUPPORT(id) DT_CLOCKS_HAS_IDX(DT_NODELABEL(id), 1) ||
459#define STM32_DT_DEV_DOMAIN_CLOCK_SUPPORT \
460 (DT_FOREACH_STATUS_OKAY(STM32_DOMAIN_CLOCK_SUPPORT) 0)
461
469#define STM32_CLOCK_REG_GET(clock) \
470 (((clock) >> STM32_CLOCK_REG_SHIFT) & STM32_CLOCK_REG_MASK)
471
477#define STM32_CLOCK_SHIFT_GET(clock) \
478 (((clock) >> STM32_CLOCK_SHIFT_SHIFT) & STM32_CLOCK_SHIFT_MASK)
479
485#define STM32_CLOCK_MASK_GET(clock) \
486 (((clock) >> STM32_CLOCK_MASK_SHIFT) & STM32_CLOCK_MASK_MASK)
487
493#define STM32_CLOCK_VAL_GET(clock) \
494 (((clock) >> STM32_CLOCK_VAL_SHIFT) & STM32_CLOCK_VAL_MASK)
495
501#define STM32_MCO_CFGR_REG_GET(mco_cfgr) \
502 (((mco_cfgr) >> STM32_MCO_CFGR_REG_SHIFT) & STM32_MCO_CFGR_REG_MASK)
503
509#define STM32_MCO_CFGR_SHIFT_GET(mco_cfgr) \
510 (((mco_cfgr) >> STM32_MCO_CFGR_SHIFT_SHIFT) & STM32_MCO_CFGR_SHIFT_MASK)
511
517#define STM32_MCO_CFGR_MASK_GET(mco_cfgr) \
518 (((mco_cfgr) >> STM32_MCO_CFGR_MASK_SHIFT) & STM32_MCO_CFGR_MASK_MASK)
519
525#define STM32_MCO_CFGR_VAL_GET(mco_cfgr) \
526 (((mco_cfgr) >> STM32_MCO_CFGR_VAL_SHIFT) & STM32_MCO_CFGR_VAL_MASK)
527
528#if defined(STM32_HSE_CSS)
537void stm32_hse_css_callback(void);
538#endif
539
540#ifdef CONFIG_SOC_SERIES_STM32WB0X
545typedef void (*lsi_update_cb_t)(uint32_t new_lsi_frequency);
546
558int stm32wb0_register_lsi_update_callback(lsi_update_cb_t cb);
559#endif /* CONFIG_SOC_SERIES_STM32WB0X */
560
561#endif /* ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_STM32_CLOCK_CONTROL_H_ */
Public Clock Control APIs.
__UINT32_TYPE__ uint32_t
Definition stdint.h:90
Driver structure definition.
Definition stm32_clock_control.h:433
uint32_t bus
Definition stm32_clock_control.h:434
uint32_t enr
Definition stm32_clock_control.h:435