NXP MCX suspend-to-RAM

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Overview

This sample exercises PM_STATE_SUSPEND_TO_RAM on NXP MCXA and MCXN SoCs, where it is mapped to the SoC Deep Power Down mode. The CORE power domain is gated and the chip wakes through the reset routine; the pm_s2ram resume path then returns directly to the suspend call site without re-running kernel or CPU initialization, so on both families the resume is transparent (resume-in-place) to the application.

A stand-in application thread models a real workload: it does its work and then blocks waiting for its next event, with no knowledge of Deep Power Down. The thread suspends the SoC to RAM and the wakeup resumes it transparently, right where it blocked. A counter incremented before every suspend survives the cycle, so the printed value demonstrates the retained RAM.

The thread repeats for CONFIG_SAMPLE_APP_TEST_CYCLES cycles (default 10) and then stops, printing a final Completed N suspend-to-RAM cycles line so a test harness can confirm every wakeup happened. No console input is needed. Once the run is over the SoC stays awake (every PM state is locked, so it only ever suspends when the sample explicitly asks it to).

The wakeup source is configured through the WUC (Wakeup Controller) subsystem and is selectable at build time:

  • CONFIG_SAMPLE_S2RAM_WAKEUP_TIMER (default) arms LPTMR0 through the counter alarm API and routes it to the core as a WUU internal-module wakeup source. The worker thread blocks in k_sleep(), so the cycle repeats automatically.

  • CONFIG_SAMPLE_S2RAM_WAKEUP_BUTTON resumes on a WUU external pin transition (the board’s wakeup-button, SW2). Deep Power Down resets the GPIO, so there is no live GPIO edge to catch on resume - the press is latched only by the WUU. The sample therefore treats the suspend-to-RAM resume itself as the wake signal (no other wakeup source is armed), observed from a PM notifier that releases the worker thread. Press SW2 to advance each cycle.

Note

On MCXN SoCs only SRAMA (the first 32 KB, retained by the VBAT RAM LDO) survives Deep Power Down, so the whole retained working set must fit in SRAMA and zephyr,sram must point to it. On MCXA SoCs all SRAM is retained by the SPC SRAM retention LDO, so no placement constraint applies.

Building and Running

west build -b frdm_mcxa156 samples/boards/nxp/mcxn_a/s2ram
west flash

Sample Output

frdm_mcxa156 suspend-to-RAM demo
Retained S2RAM cycle counter: 0
Entering suspend-to-RAM (cycle 1/10); wake in 3 s
Resumed from suspend-to-RAM; retained counter is 1
Entering suspend-to-RAM (cycle 2/10); wake in 3 s
Resumed from suspend-to-RAM; retained counter is 2
...
Entering suspend-to-RAM (cycle 10/10); wake in 3 s
Resumed from suspend-to-RAM; retained counter is 10
Completed 10 suspend-to-RAM cycles

With CONFIG_SAMPLE_S2RAM_WAKEUP_BUTTON each cycle instead waits for an SW2 press:

frdm_mcxn236 suspend-to-RAM demo
Retained S2RAM cycle counter: 0
Entering suspend-to-RAM (cycle 1/10); press SW2 to wake
Resumed from suspend-to-RAM; retained counter is 1
Entering suspend-to-RAM (cycle 2/10); press SW2 to wake
Resumed from suspend-to-RAM; retained counter is 2
...

See also

States
WUC