phyBOARD-Nash i.MX93

Overview

The phyBOARD-Nash is based on the phyCORE-i.MX93 SoM is based on the NXP i.MX93 SoC. It features common industrial interfaces and can be used as a reference for development or in the final product. It is an entry-level development board, which helps developers to get familiar with the module before investing a large amount of resources in more specific designs.

i.MX93 MPU is composed of one cluster of 2x Cortex-A55 cores and a single Cortex-M33 core. Zephyr OS is ported to run on one of the Cortex-A55 core as well as the Cortex-M33 core.

Memory:
- RAM: 512 MB - 2GB LPDDR4
- EEPROM: 4 kB - 32 kB
- eMMC: 8 GB - 256 GB
Interfaces:
- Ethernet: 2x 10/100BASE-T (1x TSN Support)
- USB: 2x 2.0 Host / OTG
- Serial: 1x RS232 / RS485 Full Duplex / Half Duplex
- CAN: 1x CAN FD
- Digital I/O: via Expansion Connector
- MMX/SD/SDIO: microSD slot
- Display: LVDS(1x4 or 1x8), MIPI DSI(1x4), HDMI
- Audio: SAI
- Camera: 1x MIPI CSI-2 (phyCAM-M), 1x Parallel
- Expansion Bus: I2C, SPI, SDIO, UART, USB
Debug:
- JTAG 10-pin connector
- USB-C for UART debug, 2x serial ports for A55 and M33

More information about the board can be found at the PHYTEC website.

Supported Features

The phyboard_nash board supports the hardware features listed below.

on-chip / on-board: Feature integrated in the SoC / present on the board.
2 / 2: Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.
vnd,foo: Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

`phyboard_nash/mimx9352/a55` target

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-A55 CPU1 1	`arm,cortex-a55`
CAN	on-chip	NXP FlexCAN CANFD controller2	`nxp,flexcan-fd`
Clock control	on-chip	i.MX CCM Rev2 (Clock Controller Module) IP node1	`nxp,imx-ccm-rev2`
Clock control	on-chip	Generic fixed-rate clock provider4	`fixed-clock`
Counter	on-chip	NXP Timer/PWM Module (TPM) used as timer6	`nxp,tpm-timer`
DAI	on-chip	NXP Synchronous Audio Interface (SAI)1	`nxp,dai-sai`
Display	on-chip	NXP i.MX LCDIFV3 (LCD Interface v3) controller1	`nxp,imx-lcdifv3`
DMA	on-chip	NXP enhanced Direct Memory Access (eDMA)1	`nxp,edma`
DMA	on-chip	NXP MCUX EDMA controller1	`nxp,mcux-edma`
Ethernet	on-chip	NXP ENET1G IP Module1	`nxp,enet1g`
	on-chip	NXP ENET MAC/L2 Device1	`nxp,enet-mac`
	on-chip	NXP ENET PTP (Precision Time Protocol) Clock1	`nxp,enet-ptp-clock`
GPIO & Headers	on-chip	i.MX RGPIO4	`nxp,imx-rgpio`
I2C	on-chip	NXP LPI2C controller8	`nxp,lpi2c`
I2S	on-chip	NXP mcux SAI-I2S controller1	`nxp,mcux-i2s`
Interrupt controller	on-chip	ARM Generic Interrupt Controller v31	`arm,gic-v3`
MDIO	on-chip	NXP ENET MDIO Features1	`nxp,enet-mdio`
MIPI-DSI	on-chip	NXP MCUX MIPI DSI DWC1	`nxp,mipi-dsi-dwc`
Miscellaneous	on-chip	NXP MCUX i.MX93 MEDIAMIX Block Control1	`nxp,imx93-mediamix`
Pin control	on-chip	This compatible binding should be applied to the device’s iomuxc DTS node1	`nxp,imx-iomuxc`
Pin control	on-chip	The node has the ‘pinctrl’ node label set in MCUX SoC’s devicetree1	`nxp,imx93-pinctrl`
Power management CPU operations	on-chip	Power State Coordination Interface (PSCI) version 1.11	`arm,psci-1.1`
SDHC	on-chip	NXP imx USDHC controller2	`nxp,imx-usdhc`
Serial controller	on-chip	NXP LPUART1 1	`nxp,lpuart`
SPI	on-chip	NXP LPSPI controller8	`nxp,lpspi`
Timer	on-chip	per-core ARM architected timer1	`arm,armv8-timer`
USB	on-chip	NXP EHCI USB device mode2	`nxp,ehci`
Watchdog	on-chip	NXP watchdog (WDOG32)2	`nxp,wdog32`

`phyboard_nash/mimx9352/m33` target

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-M33 CPU1	`arm,cortex-m33`
ADC	on-chip	NXP successive-approximation ADC (SAR ADC) controller1	`nxp,sar-adc`
ARM architecture	on-chip	i.MX ITCM (Instruction Tightly Coupled Memory)1	`nxp,imx-itcm`
ARM architecture	on-chip	i.MX DTCM (Data Tightly Coupled Memory)1	`nxp,imx-dtcm`
Clock control	on-chip	i.MX CCM Rev2 (Clock Controller Module) IP node1	`nxp,imx-ccm-rev2`
GPIO & Headers	on-chip	i.MX RGPIO4	`nxp,imx-rgpio`
I2C	on-chip	NXP LPI2C controller8	`nxp,lpi2c`
Interrupt controller	on-chip	ARMv8-M NVIC (Nested Vectored Interrupt Controller)1	`arm,v8m-nvic`
Mailbox	on-chip	NXP i.MX Message Unit as Zephyr MBOX1	`nxp,mbox-imx-mu`
MMU / MPU	on-chip	ARMv8-M MPU (Memory Protection Unit)1	`arm,armv8m-mpu`
Pin control	on-chip	This compatible binding should be applied to the device’s iomuxc DTS node1	`nxp,imx-iomuxc`
Pin control	on-chip	The node has the ‘pinctrl’ node label set in MCUX SoC’s devicetree1	`nxp,imx93-pinctrl`
PWM	on-chip	MCUX Timer/PWM Module (TPM)6	`nxp,kinetis-tpm`
Serial controller	on-chip	NXP LPUART1	`nxp,lpuart`
Timer	on-chip	ARMv8-M System Tick1	`arm,armv8m-systick`

Devices

System Clock

This board configuration uses a system clock frequency of 24 MHz. Cortex-A55 Core runs up to 1.7 GHz. Cortex-M33 Core runs up to 200MHz in which SYSTICK runs on same frequency.

Serial Port

This board configuration uses a single serial communication channel with the CPU’s UART2 for A55 core and M33 core. The u-boot bootloader or Linux use the second serial port for debug output.

Programming and Debugging (A55)

Copy the compiled zephyr.bin to the BOOT partition of the SD card and plug the SD card into the board. Power it up and stop the u-boot execution at prompt.

Use U-Boot to load and execute zephyr.bin on Cortex-A55 Core0:

fatload mmc 1:1 0xd0000000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0xd0000000

Use this configuration to run basic Zephyr applications and kernel tests, for example:

# From the root of the zephyr repository
west build -b phyboard_nash/mimx9352/a55 samples/hello_world

Use this configuration to run basic Zephyr applications, for example:

*** Booting Zephyr OS build v3.7.0-848-gb4d99b124c6d ***
Hello World! phyboard_nash/mimx9352/a55

Programming and Debugging (M33)

Copy the compiled zephyr.bin to the BOOT partition of the SD card and plug the SD card into the board. Power it up and stop the u-boot execution at prompt.

Use U-Boot to load and kick zephyr.bin to Cortex-M33 Core:

load mmc 1:1 0x80000000 zephyr.bin;cp.b 0x80000000 0x201e0000 0x30000;bootaux 0x1ffe0000 0

Use this configuration to run basic Zephyr applications, for example:

# From the root of the zephyr repository
west build -b phyboard_nash/mimx9352/m33 samples/hello_world

This will build an image with the synchronization sample app, boot it and display the following console output:

*** Booting Zephyr OS build v3.7.0-848-gb4d99b124c6d ***
Hello World! phyboard_nash/mimx9352/m33

Starting the M33-Core from U-Boot and Linux

Loading binaries and starting the M33-Core is supported from Linux via remoteproc. Please check the phyCORE-i.MX93 BSP Manual for more information.

References

For more information refer to the PHYTEC website.

phyBOARD-Nash i.MX93