FRDM-MCXW72
Overview
The FRDM-MCXW72
The MCX W72x family features a 96 MHz Arm® Cortex®-M33 core coupled with a multiprotocol radio subsystem supporting Matter, Thread, Zigbee and Bluetooth LE. The independent radio subsystem, with a dedicated core and memory, offloads the main CPU, preserving it for the primary application and allowing firmware updates to support future wireless standards.
Hardware
MCXW72 Arm Cortex-M33 microcontroller running up to 96 MHz
2MB on-chip Flash memory unit
256 KB TCM RAM
On-board MCU-Link debugger with CMSIS-DAP
For more information about the MCXW72 SoC and FRDM-MCXW72 board, see:
Supported Features
The frdm_mcxw72 board supports the hardware features listed below.
- on-chip / on-board
- Feature integrated in the SoC / present on the board.
- 2 / 2
-
Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files. -
vnd,foo -
Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.
Type |
Location |
Description |
Compatible |
|---|---|---|---|
CPU |
on-chip |
ARM Cortex-M33F CPU1 |
|
ADC |
on-chip |
LPC LPADC1 |
|
ARM architecture |
on-chip |
NXP NBU interruption information1 |
|
Bluetooth |
on-chip |
NXP BLE HCI information1 |
|
CAN |
on-chip |
NXP FlexCAN controller1 |
|
Clock control |
on-chip |
NXP K4 Generation SCG (System Clock Generator) IP node1 |
|
Counter |
on-chip |
||
Flash controller |
on-chip |
NXP MSF1 Flash Memory Module (FMU)1 |
|
GPIO & Headers |
on-chip |
||
I2C |
on-chip |
||
IEEE 802.15.4 |
on-chip |
NXP MCXW71 IEEE 802.15.4 node1 |
|
Input |
on-board |
Group of GPIO-bound input keys1 |
|
Interrupt controller |
on-chip |
ARMv8-M NVIC (Nested Vectored Interrupt Controller)1 |
|
LED |
on-board |
Group of GPIO-controlled LEDs1 |
|
on-board |
Group of PWM-controlled LEDs1 |
||
MMU / MPU |
on-chip |
ARMv8-M MPU (Memory Protection Unit)1 |
|
MTD |
on-chip |
Flash node1 |
|
on-board |
Fixed partitions of a flash (or other non-volatile storage) memory1 |
||
Pin control |
on-chip |
NXP PORT Pin Controller4 |
|
on-chip |
NXP PORT Pin Controller1 |
||
PWM |
on-chip |
||
Regulator |
on-chip |
NXP VREF SOC peripheral1 |
|
RNG |
on-chip |
NXP ELE (EdgeLock secure enclave) TRNG (True Random Number Generator)1 |
|
RTC |
on-chip |
NXP Real Time Clock (RTC)1 |
|
Sensors |
on-board |
FXLS8974 3-axis accelerometer sensor1 |
|
Serial controller |
on-chip |
NXP LPUART2 |
|
SPI |
on-chip |
||
SRAM |
on-chip |
Generic on-chip SRAM description2 |
|
Timer |
on-chip |
ARMv8-M System Tick1 |
|
Watchdog |
on-chip |
Programming and Debugging
Build and flash applications as usual (see Building an Application and Run an Application for more details).
Configuring a Debug Probe
A debug probe is used for both flashing and debugging the board. This board is configured by default to use the MCU-Link CMSIS-DAP Onboard Debug Probe.
Using LinkServer
Linkserver is the default runner for this board, and supports the factory
default MCU-Link firmware. Follow the instructions in
MCU-Link CMSIS-DAP Onboard Debug Probe to reprogram the default MCU-Link
firmware. This only needs to be done if the default onboard debug circuit
firmware was changed. To put the board in DFU mode to program the firmware,
short jumper JP5.
Using J-Link
There are two options. The onboard debug circuit can be updated with Segger
J-Link firmware by following the instructions in
MCU-Link JLink Onboard Debug Probe.
To be able to program the firmware, you need to put the board in DFU mode
by shortening the jumper JP5.
The second option is to attach a J-Link External Debug Probe to the
10-pin SWD connector (J12) of the board.
For both options use the -r jlink option with west to use the jlink runner.
west flash -r jlink
Configuring a Console
Connect a USB cable from your PC to J14, and use the serial terminal of your choice (minicom, putty, etc.) with the following settings:
Speed: 115200
Data: 8 bits
Parity: None
Stop bits: 1
Flashing
Here is an example for the Hello World application.
# From the root of the zephyr repository
west build -b frdm_mcxw72/mcxw727c/cpu0 samples/hello_world
west flash
Open a serial terminal, reset the board (press the RESET button), and you should see the following message in the terminal:
*** Booting Zephyr OS build v3.7.0-xxx-xxxx ***
Hello World! frdm_mcxw72/mcxw727c/cpu0
Debugging
Here is an example for the Hello World application.
# From the root of the zephyr repository
west build -b frdm_mcxw72/mcxw727c/cpu0 samples/hello_world
west debug
Open a serial terminal, step through the application in your debugger, and you should see the following message in the terminal:
*** Booting Zephyr OS build v3.7.0-xxx-xxxx ***
Hello World! frdm_mcxw72/mcxw727c/cpu0
Troubleshooting
Using Segger SystemView and RTT
Note that when using SEGGER SystemView or RTT with this SOC, the RTT control
block address must be set manually within SystemView or the RTT Viewer. The
address provided to the tool should be the location of the _SEGGER_RTT
symbol, which can be found using a debugger or by examining the zephyr.map
file output by the linker.
The RTT control block address must be provided manually because this SOC supports ECC RAM. If the SEGGER tooling searches the ECC RAM space for the control block a fault will occur, provided that ECC is enabled and the RAM segment being searched has not been initialized to a known value.
Support Resources for Zephyr
MCUXpresso for VS Code [2], wiki [3] documentation and Zephyr lab guides [4]
NXP’s Zephyr landing page [6] (including training resources)