MIMXRT1064-EVK

Board Overview

MIMXRT1064-EVK

Name:

mimxrt1064_evk

Vendor:

NXP Semiconductors

Architecture:

arm

SoC:

mimxrt1064

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Overview

The i.MX RT1064 adds to the industry’s first crossover processor series and expands the i.MX RT series to three scalable families. The i.MX RT1064 doubles the On-Chip SRAM to 1MB while keeping pin-to-pin compatibility with i.MX RT1050. This series introduces additional features ideal for real-time applications such as High-Speed GPIO, CAN FD, and synchronous parallel NAND/NOR/PSRAM controller. The i.MX RT1064 runs on the Arm® Cortex-M7® core up to 600 MHz.

Hardware

• MIMXRT1064DVL6A MCU (600 MHz, 1024 KB on-chip memory, 4096KB on-chip QSPI flash)

• Memory

  • 256 Mbit SDRAM

  • 64 Mbit QSPI Flash

  • 512 Mbit Hyper Flash

  • TF socket for SD card

• Display

  • LCD connector

• Ethernet

  • 10/100 Mbit/s Ethernet PHY

• USB

  • USB 2.0 OTG connector

  • USB 2.0 host connector

• Audio

  • 3.5 mm audio stereo headphone jack

  • Board-mounted microphone

  • Left and right speaker out connectors

• Power

  • 5 V DC jack

• Debug

  • JTAG 20-pin connector

  • OpenSDA with DAPLink

• Sensor

  • FXOS8700CQ 6-axis e-compass

  • CMOS camera sensor interface

• Expansion port

  • Arduino interface

• CAN bus connector

For more information about the MIMXRT1064 SoC and MIMXRT1064-EVK board, see these references:

• i.MX RT1064 Website

• i.MX RT1064 Datasheet

• i.MX RT1064 Reference Manual

• MIMXRT1064-EVK Website

• MIMXRT1064-EVK Quick Reference Guide

• MIMXRT1064-EVK User Guide

• MIMXRT1064-EVK Schematics

• MIMXRT1064-EVK Debug Firmware

External Memory

This platform has the following external memories:

Device	Controller	Status
MT48LC16M16A2	SEMC	Enabled via device configuration data block, which sets up SEMC at boot time

Supported Features

NXP considers the MIMXRT1064-EVK as the superset board for the i.MX RT10xx family of MCUs. This board is a focus for NXP’s Full Platform Support for Zephyr, to better enable the entire RT10xx family. NXP prioritizes enabling this board with new support for Zephyr features.

The mimxrt1064_evk board supports the hardware features listed below.

on-chip / on-board

Feature integrated in the SoC / present on the board.

2 / 2

Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.

vnd,foo

Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

mimxrt1064_evk

/

mimxrt1064

mimxrt1064_evk/mimxrt1064 target

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-M7 CPU1	arm,cortex-m7
ADC	on-chip	NXP MCUA 12B1MSPS SAR ADC1 1	nxp,mcux-12b1msps-sar
ARM architecture	on-chip	MCUX XBAR (Crossbar)3	nxp,mcux-xbar
CAN	on-chip	NXP FlexCAN controller1 1	nxp,flexcan
	on-chip	NXP FlexCAN CANFD controller1	nxp,flexcan-fd
Clock control	on-chip	i.MX CCM (Clock Controller Module) IP node1	nxp,imx-ccm
	on-chip	Generic fixed factor clock provider3	fixed-factor-clock
	on-chip	i.MX CCM Fractional PLL1	nxp,imx-ccm-fnpll
	on-chip	i.MX ANATOP (Analog Clock Controller Module) IP node1	nxp,imx-anatop
	on-chip	Generic fixed-rate clock provider4	fixed-clock
Counter	on-chip	NXP MCUX Quad Timer (QTMR)4	nxp,imx-qtmr
	on-chip	NXP MCUX Quad Timer Channel16	nxp,imx-tmr
	on-chip	NXP Periodic Interrupt Timer (PIT)1	nxp,pit
	on-chip	Child node for the Periodic Interrupt Timer node, intended for an individual timer channel4	nxp,pit-channel
Cryptographic accelerator	on-chip	NXP Data Co-Processor (DCP) Crypto accelerator1	nxp,mcux-dcp
Debug	on-chip	ARMv7 instrumentation trace macrocell1	arm,armv7m-itm
Display	on-chip	NXP i.MX eLCDIF (Enhanced LCD Interface) controller1	nxp,imx-elcdif
DMA	on-chip	NXP MCUX EDMA controller1	nxp,mcux-edma
	on-chip	NXP PXP 2D DMA engine1	nxp,pxp
Ethernet	on-chip	NXP ENET IP Module2	nxp,enet
	on-chip	NXP ENET MAC/L2 Device1 1	nxp,enet-mac
	on-board	Microchip KSZ8081 Ethernet PHY device1	microchip,ksz8081
	on-chip	NXP ENET PTP (Precision Time Protocol) Clock1 1	nxp,enet-ptp-clock
GPIO & Headers	on-chip	i.MX GPIO9	nxp,imx-gpio
	on-board	GPIO pins exposed on NXP LCD interface1	nxp,parallel-lcd-connector
	on-board	GPIO pins exposed on NXP LCD touch controller interface1	nxp,i2c-tsc-fpc
	on-board	GPIO pins exposed on Arduino Uno (R3) headers1	arduino-header-r3
I2C	on-chip	NXP LPI2C controller1 3	nxp,lpi2c
I2S	on-chip	NXP mcux SAI-I2S controller3	nxp,mcux-i2s
Input	on-board	FT3267/FT5XX6/FT6XX6 capacitive touch panels1	focaltech,ft5336
	on-board	Group of GPIO-bound input keys1	gpio-keys
Interrupt controller	on-chip	ARMv7-M NVIC (Nested Vectored Interrupt Controller)1	arm,v7m-nvic
LED	on-board	Group of GPIO-controlled LEDs1	gpio-leds
	on-board	Group of PWM-controlled LEDs1	pwm-leds
MDIO	on-chip	NXP ENET MDIO Features1 1	nxp,enet-mdio
Memory controller	on-chip	NXP FlexRAM on-chip ram controller If the flexram,bank-spec property is specified, then the flexram will be dynamically reconfigured to the configuration specified at runtime1	nxp,flexram
	on-chip	NXP Smart External Memory Controller (SEMC)1	nxp,imx-semc
Miscellaneous	on-chip	NXP FlexIO controller3	nxp,flexio
MMU / MPU	on-chip	ARMv7-M Memory Protection Unit (MPU)1	arm,armv7m-mpu
MTD	on-board	NXP FlexSPI NOR2	nxp,imx-flexspi-nor
	on-board	Fixed partitions of a flash (or other non-volatile storage) memory2	fixed-partitions
Pin control	on-chip	This compatible binding should be applied to the device’s iomuxc DTS node1	nxp,imx-iomuxc
	on-chip	The node has the ‘pinctrl’ node label set in MCUX RT SoC’s devicetree1	nxp,mcux-rt-pinctrl
	on-chip	i.MX IOMUXC1	nxp,imx-gpr
PWM	on-chip	NXP eFLEX PWM module with mcux-pwm submodules4	nxp,flexpwm
	on-chip	NXP MCUX PWM1 15	nxp,imx-pwm
RNG	on-chip	Kinetis TRNG (True Random Number Generator)1	nxp,kinetis-trng
RTC	on-chip	NXP SNVS LP/HP RTC1	nxp,imx-snvs-rtc
SDHC	on-chip	NXP imx USDHC controller1 1	nxp,imx-usdhc
Sensors	on-chip	NXP MCUX QDEC4	nxp,mcux-qdec
	on-chip	NXP on-die temperature monitor1	nxp,tempmon
Serial controller	on-chip	NXP LPUART1 7	nxp,lpuart
SPI	on-chip	NXP FlexSPI controller2	nxp,imx-flexspi
	on-chip	NXP LPSPI controller2 2	nxp,lpspi
Timer	on-chip	ARMv7-M System Tick1	arm,armv7m-systick
	on-chip	NXP MCUX General-Purpose HW Timer (GPT)1	nxp,gpt-hw-timer
	on-chip	NXP MCUX General-Purpose Timer (GPT)1	nxp,imx-gpt
USB	on-chip	NXP EHCI USB device mode1 1	nxp,ehci
	on-chip	NXP USB high speed phy that is used on NXP RTxxxx, RTxxx, MCX, LPC and Kinetis platforms if high speed usb is supported on these platforms2	nxp,usbphy
Video	on-chip	NXP MCUX CMOS sensor interface1	nxp,imx-csi
Watchdog	on-chip	imxRT watchdog1 1	nxp,imx-wdog

Connections and I/Os

The MIMXRT1064 SoC has four pairs of pinmux/gpio controllers.

Name	Function	Usage
GPIO_AD_B0_00	LPSPI1_SCK	SPI
GPIO_AD_B0_01	LPSPI1_SDO	SPI
GPIO_AD_B0_02	LPSPI3_SDI/LCD_RST| SPI/LCD Display
GPIO_AD_B0_03	LPSPI3_PCS0	SPI
GPIO_AD_B0_05	GPIO	SD Card
GPIO_AD_B0_09	GPIO/ENET_RST	LED/Ethernet
GPIO_AD_B0_10	GPIO/ENET_INT	GPIO/Ethernet
GPIO_AD_B0_11	GPIO	Touch Interrupt
GPIO_AD_B0_12	LPUART1_TX	UART Console
GPIO_AD_B0_13	LPUART1_RX	UART Console
GPIO_AD_B1_06	LPUART3_TX	UART Arduino
GPIO_AD_B1_07	LPUART3_RX	UART Arduino
WAKEUP	GPIO	SW0
GPIO_B0_00	LCD_CLK	LCD Display
GPIO_B0_01	LCD_ENABLE	LCD Display
GPIO_B0_02	LCD_HSYNC	LCD Display
GPIO_B0_03	LCD_VSYNC	LCD Display
GPIO_B0_04	LCD_DATA00	LCD Display
GPIO_B0_05	LCD_DATA01	LCD Display
GPIO_B0_06	LCD_DATA02	LCD Display
GPIO_B0_07	LCD_DATA03	LCD Display
GPIO_B0_08	LCD_DATA04	LCD Display
GPIO_B0_09	LCD_DATA05	LCD Display
GPIO_B0_10	LCD_DATA06	LCD Display
GPIO_B0_11	LCD_DATA07	LCD Display
GPIO_B0_12	LCD_DATA08	LCD Display
GPIO_B0_13	LCD_DATA09	LCD Display
GPIO_B0_14	LCD_DATA10	LCD Display
GPIO_B0_15	LCD_DATA11	LCD Display
GPIO_B1_00	LCD_DATA12	LCD Display
GPIO_B1_01	LCD_DATA13	LCD Display
GPIO_B1_02	LCD_DATA14	LCD Display
GPIO_B1_03	LCD_DATA15	LCD Display
GPIO_B1_04	ENET_RX_DATA00	Ethernet
GPIO_B1_05	ENET_RX_DATA01	Ethernet
GPIO_B1_06	ENET_RX_EN	Ethernet
GPIO_B1_07	ENET_TX_DATA00	Ethernet
GPIO_B1_08	ENET_TX_DATA01	Ethernet
GPIO_B1_09	ENET_TX_EN	Ethernet
GPIO_B1_10	ENET_REF_CLK	Ethernet
GPIO_B1_11	ENET_RX_ER	Ethernet
GPIO_B1_12	GPIO	SD Card
GPIO_B1_14	USDHC1_VSELECT	SD Card
GPIO_B1_15	BACKLIGHT_CTL	LCD Display
GPIO_EMC_40	ENET_MDC	Ethernet
GPIO_EMC_41	ENET_MDIO	Ethernet
GPIO_AD_B0_09	ENET_RST	Ethernet
GPIO_AD_B0_10	ENET_INT	Ethernet
GPIO_SD_B0_00	USDHC1_CMD/LPSPI1_SCK | SD Card/SPI
GPIO_SD_B0_01	USDHC1_CLK/LPSPI1_PCS0 | SD Card/SPI
GPIO_SD_B0_02	USDHC1_DATA0/LPSPI1_SDO | SD Card/SPI
GPIO_SD_B0_03	USDHC1_DATA1/LPSPI1_SDI | SD Card/SPI
GPIO_SD_B0_04	USDHC1_DATA2	SD Card
GPIO_SD_B0_05	USDHC1_DATA3	SD Card
GPIO_SD_B1_05	FLEXSPIA_DQS	QSPI Flash
GPIO_SD_B1_06	FLEXSPIA_SS0_B	QSPI Flash
GPIO_SD_B1_07	FLEXSPIA_SCLK	QSPI Flash
GPIO_SD_B1_08	FLEXSPIA_DATA00	QSPI Flash
GPIO_SD_B1_09	FLEXSPIA_DATA01	QSPI Flash
GPIO_SD_B1_10	FLEXSPIA_DATA02	QSPI Flash
GPIO_SD_B1_11	FLEXSPIA_DATA03	QSPI Flash
GPIO_AD_B1_11	ADC	ADC1 Channel 0
GPIO_AD_B1_10	ADC	ADC1 Channel 1

Note

In order to use the SPI peripheral on this board, resistors R278, R279, R280 and R281 must be populated with zero ohm resistors

System Clock

The MIMXRT1064 SoC is configured to use SysTick as the system clock source, running at 600MHz.

When power management is enabled, the 32 KHz low frequency oscillator on the board will be used as a source for the GPT timer to generate a system clock. This clock enables lower power states, at the cost of reduced resolution

Serial Port

The MIMXRT1064 SoC has eight UARTs. LPUART1 is configured for the console and the remaining are not used.

Programming and Debugging

This board supports 3 debug host tools. Please install your preferred host tool, then follow the instructions in Configuring a Debug Probe to configure the board appropriately.

• J-Link Debug Host Tools (Default, Supported by NXP)

• LinkServer Debug Host Tools (Supported by NXP)

• pyOCD Debug Host Tools (Not supported by NXP)

Once the host tool and board are configured, build and flash applications as usual (see Building an Application and Run an Application for more details).

Configuring a Debug Probe

Note

When the device transitions into low power states, the debugger may be unable to access the chip. Use caution when enabling CONFIG_PM, and if the debugger cannot flash the part, see Troubleshooting

For the RT1064, J47/J48 are the SWD isolation jumpers, J42 is the DFU mode jumper, and J21 is the 20 pin JTAG/SWD header.

A debug probe is used for both flashing and debugging the board. This board has an LPC-LINK2 Onboard Debug Probe. The default firmware present on this probe is the LPC-Link2 DAPLink Onboard Debug Probe.

Based on the host tool installed, please use the following instructions to setup your debug probe:

• J-Link Debug Host Tools: Using J-Link with LPC-Link2 Probe

• LinkServer Debug Host Tools: Using CMSIS-DAP with LPC-Link2 Probe

• pyOCD Debug Host Tools: Using CMSIS-DAP with LPC-Link2 Probe

Using CMSIS-DAP with LPC-Link2 Probe

1. Follow the instructions provided at LPC-LINK2 CMSIS DAP Onboard Debug Probe to reprogram the default debug probe firmware on this board.

2. Ensure the SWD isolation jumpers are populated

Using J-Link with LPC-Link2 Probe

There are two options: the onboard debug circuit can be updated with Segger J-Link firmware, or a J-Link External Debug Probe can be attached to the EVK.

To update the onboard debug circuit, please do the following:

1. Switch the power source for the EVK to a different source than the debug USB, as the J-Link firmware does not power the EVK via the debug USB.

2. Follow the instructions provided at LPC-Link2 J-Link Onboard Debug Probe to reprogram the default debug probe firmware on this board.

3. Ensure the SWD isolation jumpers are populated.

To attach an external J-Link probe, ensure the SWD isolation jumpers are removed, then connect the probe to the external JTAG/SWD header

See Using J-Link with MIMXRT1060-EVK or MIMXRT1064-EVK for more details.

Configuring a Console

Regardless of your choice in debug probe, we will use the OpenSDA microcontroller as a usb-to-serial adapter for the serial console. Check that jumpers J45 and J46 are on (they are on by default when boards ship from the factory) to connect UART signals to the OpenSDA microcontroller.

Connect a USB cable from your PC to J41.

Use the following settings with your serial terminal of choice (minicom, putty, etc.):

• Speed: 115200

• Data: 8 bits

• Parity: None

• Stop bits: 1

Using SWO

SWO can be used as a logging backend, by setting CONFIG_LOG_BACKEND_SWO=y. Your SWO viewer should be configured with a CPU frequency of 132MHz, and SWO frequency of 7500KHz.

Flashing

Here is an example for the Hello World application.

# From the root of the zephyr repository
west build -b mimxrt1064_evk samples/hello_world
west flash

Open a serial terminal, reset the board (press the SW9 button), and you should see the following message in the terminal:

***** Booting Zephyr OS v1.14.0-rc1 *****
Hello World! mimxrt1064_evk

Debugging

Here is an example for the Hello World application.

# From the root of the zephyr repository
west build -b mimxrt1064_evk samples/hello_world
west debug

Open a serial terminal, step through the application in your debugger, and you should see the following message in the terminal:

***** Booting Zephyr OS v1.14.0-rc1 *****
Hello World! mimxrt1064_evk

Troubleshooting

If the debug probe fails to connect with the following error, it’s possible that the boot header in QSPI flash is invalid or corrupted. The boot header is configured by CONFIG_NXP_IMXRT_BOOT_HEADER.

Remote debugging using :2331
Remote communication error.  Target disconnected.: Connection reset by peer.
"monitor" command not supported by this target.
"monitor" command not supported by this target.
You can't do that when your target is `exec'
(gdb) Could not connect to target.
Please check power, connection and settings.

You can fix it by erasing and reprogramming the QSPI flash with the following steps:

1. Set the SW7 DIP switches to ON-OFF-ON-OFF to prevent booting from QSPI flash.

2. Reset by pressing SW9

3. Run west debug or west flash again with a known working Zephyr application.

4. Set the SW7 DIP switches to OFF-OFF-ON-OFF to boot from QSPI flash.

5. Reset by pressing SW9

If the west flash or debug commands fail, and the command hangs while executing runners.jlink, confirm the J-Link debug probe is configured, powered, and connected to the EVK properly.

Support Resources for Zephyr

• NXP Zephyr Downstream Software Development Kit

• MCUXpresso for VS Code, wiki documentation and Zephyr lab guides

• NXP Zephyr Knowledge Hub

• NXP’s Zephyr landing page (including training resources)

• NXP Support Community forum for Zephyr