i.MX8MN EVK (Cortex-A53)

Board Overview

Name:

imx8mn_evk

Vendor:

NXP Semiconductors

Architecture:

arm64

SoC:

mimx8mn6

Browse board sources

Overview

i.MX8M Nano LPDDR4 EVK board is based on NXP i.MX8M Nano applications processor, composed of a quad Cortex®-A53 cluster and a single Cortex®-M7 core. Zephyr OS is ported to run on the Cortex®-A53 core.

• Board features:

  • RAM: 2GB LPDDR4

  • Storage:

    • SanDisk 16GB eMMC5.1

    • Micron 32MB QSPI NOR

    • microSD Socket

  • Wireless:

    • WiFi: 2.4/5GHz IEEE 802.11b/g/n

    • Bluetooth: v4.1

  • USB:

    • OTG - 2x type C

  • Ethernet

  • PCI-E M.2

  • Connectors:

    • 40-Pin Dual Row Header

  • LEDs:

    • 1x Power status LED

    • 1x UART LED

  • Debug

    • JTAG 20-pin connector

    • MicroUSB for UART debug, two COM ports for A53 and M7

More information about the board can be found at the NXP website.

Supported Features

The imx8mn_evk board supports the hardware features listed below.

on-chip / on-board

Feature integrated in the SoC / present on the board.

2 / 2

Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.

vnd,foo

Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

imx8mn_evk

/

mimx8mn6/a53mimx8mn6/a53/smp

imx8mn_evk/mimx8mn6/a53 target

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-A53 CPU1 3	arm,cortex-a53
Clock control	on-chip	i.MX CCM (Clock Controller Module) IP node1	nxp,imx-ccm
Ethernet	on-chip	NXP ENET1G IP Module1	nxp,enet1g
	on-chip	NXP ENET MAC/L2 Device1	nxp,enet-mac
	on-board	Qualcomm Atheros AR8031 Ethernet PHY1	qca,ar8031
	on-chip	NXP ENET PTP (Precision Time Protocol) Clock1	nxp,enet-ptp-clock
GPIO & Headers	on-chip	i.MX GPIO1 4	nxp,imx-gpio
	on-board	PCA6416 I2C-based GPIO expander1	nxp,pca6416
I2C	on-chip	NXP II2C1 3	nxp,ii2c
Interrupt controller	on-chip	ARM Generic Interrupt Controller v31	arm,gic-v3
MDIO	on-chip	NXP ENET MDIO Features1	nxp,enet-mdio
Miscellaneous	on-chip	NXP i.MX Resource Domain Controller (RDC)1	nxp,rdc
Pin control	on-chip	This compatible binding should be applied to the device’s iomuxc DTS node1	nxp,imx-iomuxc
	on-chip	The node has the ‘pinctrl’ node label set in MCUX SoC’s devicetree1	nxp,imx8mp-pinctrl
Serial controller	on-chip	This binding gives a base representation of the NXP iMX IUART1 1	nxp,imx-iuart
Timer	on-chip	per-core ARM architected timer1	arm,armv8-timer
	on-chip	NXP MCUX General-Purpose Timer (GPT)2	nxp,imx-gpt

imx8mn_evk/mimx8mn6/a53/smp target

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-A53 CPU2 2	arm,cortex-a53
Clock control	on-chip	i.MX CCM (Clock Controller Module) IP node1	nxp,imx-ccm
Ethernet	on-chip	NXP ENET1G IP Module1	nxp,enet1g
	on-chip	NXP ENET MAC/L2 Device1	nxp,enet-mac
	on-board	Qualcomm Atheros AR8031 Ethernet PHY1	qca,ar8031
	on-chip	NXP ENET PTP (Precision Time Protocol) Clock1	nxp,enet-ptp-clock
GPIO & Headers	on-chip	i.MX GPIO5	nxp,imx-gpio
I2C	on-chip	NXP II2C4	nxp,ii2c
Interrupt controller	on-chip	ARM Generic Interrupt Controller v31	arm,gic-v3
MDIO	on-chip	NXP ENET MDIO Features1	nxp,enet-mdio
Miscellaneous	on-chip	NXP i.MX Resource Domain Controller (RDC)1	nxp,rdc
Pin control	on-chip	This compatible binding should be applied to the device’s iomuxc DTS node1	nxp,imx-iomuxc
	on-chip	The node has the ‘pinctrl’ node label set in MCUX SoC’s devicetree1	nxp,imx8mp-pinctrl
Power management CPU operations	on-board	Power State Coordination Interface (PSCI) version 0.21	arm,psci-0.2
Serial controller	on-chip	This binding gives a base representation of the NXP iMX IUART1 1	nxp,imx-iuart
Timer	on-chip	per-core ARM architected timer1	arm,armv8-timer
	on-chip	NXP MCUX General-Purpose Timer (GPT)2	nxp,imx-gpt

Devices

System Clock

This board configuration uses a system clock frequency of 8 MHz.

Serial Port

This board configuration uses a single serial communication channel with the CPU’s UART4.

Programming and Debugging

U-Boot “cpu” command is used to load and kick Zephyr to Cortex-A secondary Core, Currently it has been supported in latest U-Boot version by patch serials.

Copy the compiled zephyr.bin to the first FAT partition of the SD card and plug the SD card into the board. Power it up and stop the u-boot execution at prompt.

Use U-Boot to load and kick zephyr.bin to Cortex-A53 Core0:

fatload mmc 1:1 0x93c00000 zephyr.bin; dcache flush; icache flush; go 0x93c00000

Or kick zephyr.bin to the other Cortex-A53 Core, for example Core2:

fatload mmc 1:1 0x93c00000 zephyr.bin; dcache flush; icache flush; cpu 2 release 0x93c00000

Use this configuration to run basic Zephyr applications and kernel tests, for example, with the Basic Synchronization sample:

# From the root of the zephyr repository
west build -b imx8mn_evk/mimx8mn6/a53 samples/synchronization
west build -t run

This will build an image with the synchronization sample app, boot it and display the following ram console output:

*** Booting Zephyr OS build zephyr-v3.1.0-3575-g44dd713bd883  ***
thread_a: Hello World from cpu 0 on mimx8mn_evk_a53!
thread_b: Hello World from cpu 0 on mimx8mn_evk_a53!
thread_a: Hello World from cpu 0 on mimx8mn_evk_a53!
thread_b: Hello World from cpu 0 on mimx8mn_evk_a53!
thread_a: Hello World from cpu 0 on mimx8mn_evk_a53!

Use Jailhouse hypervisor, after root cell linux is up:

#jailhouse enable imx8mn.cell
#jailhouse cell create imx8mn-zephyr.cell
#jailhouse cell load 1 zephyr.bin -a 0x93c00000
#jailhouse cell start 1

Support Resources for Zephyr

• NXP Zephyr Downstream Software Development Kit

• MCUXpresso for VS Code, wiki documentation and Zephyr lab guides

• NXP Zephyr Knowledge Hub

• NXP’s Zephyr landing page (including training resources)

• NXP Support Community forum for Zephyr