LPCXPRESSO55S69

Board Overview

LPCXPRESSO55S69

Name:

lpcxpresso55s69

Vendor:

NXP Semiconductors

Architecture:

arm

SoC:

lpc55s69

Browse board sources

Overview

The LPCXpresso55S69 development board provides the ideal platform for evaluation of and development with the LPC55S6x MCU based on the Arm® Cortex®-M33 architecture. The board includes a high performance onboard debug probe, audio subsystem, and accelerometer, with several options for adding off-the-shelf add-on boards for networking, sensors, displays, and other interfaces.

Hardware

• LPC55S69 dual core Arm Cortex-M33 microcontroller running at up to 100 MHz

• Onboard, high-speed USB, Link2 debug probe with CMSIS-DAP and SEGGER J-Link protocol options

• UART and SPI port bridging from LPC55S69 target to USB via the onboard debug probe

• Hardware support for external debug probe

• 3 x user LEDs, plus Reset, ISP (3) and user buttons

• Micro SD card slot (4-bit SDIO)

• NXP MMA8652FCR1 accelerometer

• Stereo audio codec with line in/out

• High and full speed USB ports with micro A/B connector for host or device functionality

• MikroEletronika Click expansion option

• LPCXpresso-V3 expansion option compatible with Arduino UNO

• PMod compatible expansion / host connector

For more information about the LPC55S69 SoC and LPCXPRESSO55S69 board, see:

• LPC55S69 SoC Website

• LPC55S69 Datasheet

• LPC55S69 Reference Manual

• LPCXPRESSO55S69 Website

• LPCXPRESSO55S69 User Guide

• LPCXPRESSO55S69 Schematics

• LPCXPRESSO55S69 Debug Firmware

Supported Features

NXP considers the LPCXpresso55S69 as the superset board for the LPC55xx series of MCUs. This board is a focus for NXP’s Full Platform Support for Zephyr, to better enable the entire LPC55xx series. NXP prioritizes enabling this board with new support for Zephyr features.

The lpcxpresso55s69 board supports the hardware features listed below.

on-chip / on-board

Feature integrated in the SoC / present on the board.

2 / 2

Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.

vnd,foo

Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

lpcxpresso55s69

/

lpc55s69/cpu0lpc55s69/cpu0/nslpc55s69/cpu1

lpcxpresso55s69/lpc55s69/cpu0 target

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-M33F CPU1	arm,cortex-m33f
ADC	on-chip	LPC LPADC1	nxp,lpc-lpadc
ARM architecture	on-chip	LPC Flexcomm node3	nxp,lpc-flexcomm
Clock control	on-chip	LPC SYSCON & CLKCTL IP node1	nxp,lpc-syscon
Counter	on-chip	NXP MCUX Standard Timer/Counter5	nxp,lpc-ctimer
	on-chip	NXP Multirate Timer1	nxp,mrt
	on-chip	NXP Multirate Timer Channel1 3	nxp,mrt-channel
DMA	on-chip	NXP LPC DMA controller2	nxp,lpc-dma
Flash controller	on-chip	NXP (In-Application Programming) flash memory controller for the lpc55xxx family, except lpc553x1	nxp,iap-fmc55
GPIO & Headers	on-chip	LPC GPIO1	nxp,lpc-gpio
	on-chip	LPC GPIO port device2	nxp,lpc-gpio-port
	on-board	GPIO pins exposed on Mikro BUS headers1	mikro-bus
	on-board	GPIO pins exposed on Arduino Uno (R3) headers1	arduino-header-r3
Hardware information	on-chip	NXP LPC 128-bit Unique identifier1	nxp,lpc-uid
I2C	on-chip	LPC I2C1	nxp,lpc-i2c
I2S	on-chip	LPC I2S node2	nxp,lpc-i2s
Input	on-board	Group of GPIO-bound input keys1	gpio-keys
Interrupt controller	on-chip	ARMv8-M NVIC (Nested Vectored Interrupt Controller)1	arm,v8m-nvic
	on-chip	NXP Pin interrupt and pattern match engine (PINT)1	nxp,pint
IPM	on-chip	LPC MAILBOX1	nxp,lpc-mailbox
LED	on-board	Group of GPIO-controlled LEDs1	gpio-leds
	on-board	Group of PWM-controlled LEDs1	pwm-leds
MMU / MPU	on-chip	ARMv8-M MPU (Memory Protection Unit)1	arm,armv8m-mpu
MTD	on-chip	Flash node2 1	soc-nv-flash
	on-board	Fixed partitions of a flash (or other non-volatile storage) memory1	fixed-partitions
Pin control	on-chip	LPC I/O Pin Configuration (IOCON)1	nxp,lpc-iocon
	on-chip	LPC pinctrl node1	nxp,lpc-iocon-pinctrl
PWM	on-chip	NXP SCTimer PWM1	nxp,sctimer-pwm
Reset controller	on-chip	LPC SYSCON Peripheral reset controller1	nxp,lpc-syscon-reset
RNG	on-chip	LPC RNG (Random Number Generator)1	nxp,lpc-rng
SDHC	on-chip	NXP LPC SDIF SD host controller1	nxp,lpc-sdif
Sensors	on-board	FXOS8700 6-axis accelerometer/magnetometer sensor1	nxp,fxos8700
Serial controller	on-chip	LPC USART1 1	nxp,lpc-usart
SPI	on-chip	NXP LPC SPI controller1	nxp,lpc-spi
SRAM	on-chip	Generic on-chip SRAM description6	mmio-sram
Timer	on-chip	ARMv8-M System Tick1	arm,armv8m-systick
USB	on-chip	NXP LPCIP3511 USB device mode1 1	nxp,lpcip3511
	on-chip	NXP USB high speed phy that is used on NXP RTxxxx, RTxxx, MCX, LPC and Kinetis platforms if high speed usb is supported on these platforms1	nxp,usbphy
Watchdog	on-chip	LPC Windowed Watchdog Timer1	nxp,lpc-wwdt

lpcxpresso55s69/lpc55s69/cpu0/ns target

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-M33F CPU1	arm,cortex-m33f
ADC	on-chip	LPC LPADC1	nxp,lpc-lpadc
ARM architecture	on-chip	LPC Flexcomm node5	nxp,lpc-flexcomm
Clock control	on-chip	LPC SYSCON & CLKCTL IP node1	nxp,lpc-syscon
Counter	on-chip	NXP MCUX Standard Timer/Counter5	nxp,lpc-ctimer
	on-chip	NXP Multirate Timer1	nxp,mrt
	on-chip	NXP Multirate Timer Channel4	nxp,mrt-channel
DMA	on-chip	NXP LPC DMA controller1 1	nxp,lpc-dma
Flash controller	on-chip	NXP (In-Application Programming) flash memory controller for the lpc55xxx family, except lpc553x1	nxp,iap-fmc55
GPIO & Headers	on-chip	LPC GPIO1	nxp,lpc-gpio
	on-chip	LPC GPIO port device2	nxp,lpc-gpio-port
	on-board	GPIO pins exposed on Mikro BUS headers1	mikro-bus
	on-board	GPIO pins exposed on Arduino Uno (R3) headers1	arduino-header-r3
Hardware information	on-chip	NXP LPC 128-bit Unique identifier1	nxp,lpc-uid
I2C	on-chip	LPC I2C1	nxp,lpc-i2c
Input	on-board	Group of GPIO-bound input keys1	gpio-keys
Interrupt controller	on-chip	NXP Pin interrupt and pattern match engine (PINT)1	nxp,pint
	on-chip	ARMv8-M NVIC (Nested Vectored Interrupt Controller)1	arm,v8m-nvic
IPM	on-chip	LPC MAILBOX1	nxp,lpc-mailbox
LED	on-board	Group of GPIO-controlled LEDs1	gpio-leds
MMU / MPU	on-chip	ARMv8-M MPU (Memory Protection Unit)1	arm,armv8m-mpu
MTD	on-chip	Flash node2 1	soc-nv-flash
	on-board	Fixed partitions of a flash (or other non-volatile storage) memory1	fixed-partitions
Pin control	on-chip	LPC I/O Pin Configuration (IOCON)1	nxp,lpc-iocon
	on-chip	LPC pinctrl node1	nxp,lpc-iocon-pinctrl
PWM	on-chip	NXP SCTimer PWM1	nxp,sctimer-pwm
Reset controller	on-chip	LPC SYSCON Peripheral reset controller1	nxp,lpc-syscon-reset
RNG	on-chip	LPC RNG (Random Number Generator)1	nxp,lpc-rng
SDHC	on-chip	NXP LPC SDIF SD host controller1	nxp,lpc-sdif
Sensors	on-board	FXOS8700 6-axis accelerometer/magnetometer sensor1	nxp,fxos8700
Serial controller	on-chip	LPC USART1 1	nxp,lpc-usart
SPI	on-chip	NXP LPC SPI controller1	nxp,lpc-spi
SRAM	on-chip	Generic on-chip SRAM description6	mmio-sram
Timer	on-chip	ARMv8-M System Tick1	arm,armv8m-systick
USB	on-chip	NXP LPCIP3511 USB device mode1 1	nxp,lpcip3511
	on-chip	NXP USB high speed phy that is used on NXP RTxxxx, RTxxx, MCX, LPC and Kinetis platforms if high speed usb is supported on these platforms1	nxp,usbphy
Watchdog	on-chip	LPC Windowed Watchdog Timer1	nxp,lpc-wwdt

lpcxpresso55s69/lpc55s69/cpu1 target

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-M33 CPU1	arm,cortex-m33
ADC	on-chip	LPC LPADC1	nxp,lpc-lpadc
ARM architecture	on-chip	LPC Flexcomm node5	nxp,lpc-flexcomm
Clock control	on-chip	LPC SYSCON & CLKCTL IP node1	nxp,lpc-syscon
Counter	on-chip	NXP MCUX Standard Timer/Counter5	nxp,lpc-ctimer
	on-chip	NXP Multirate Timer1	nxp,mrt
	on-chip	NXP Multirate Timer Channel4	nxp,mrt-channel
DMA	on-chip	NXP LPC DMA controller2	nxp,lpc-dma
Flash controller	on-chip	NXP (In-Application Programming) flash memory controller for the lpc55xxx family, except lpc553x1	nxp,iap-fmc55
GPIO & Headers	on-chip	LPC GPIO1	nxp,lpc-gpio
	on-chip	LPC GPIO port device2	nxp,lpc-gpio-port
	on-board	GPIO pins exposed on Mikro BUS headers1	mikro-bus
	on-board	GPIO pins exposed on Arduino Uno (R3) headers1	arduino-header-r3
Hardware information	on-chip	NXP LPC 128-bit Unique identifier1	nxp,lpc-uid
I2C	on-chip	LPC I2C1	nxp,lpc-i2c
Interrupt controller	on-chip	NXP Pin interrupt and pattern match engine (PINT)1	nxp,pint
	on-chip	ARMv8-M NVIC (Nested Vectored Interrupt Controller)1	arm,v8m-nvic
IPM	on-chip	LPC MAILBOX1	nxp,lpc-mailbox
LED	on-board	Group of GPIO-controlled LEDs1	gpio-leds
MTD	on-chip	Flash node2 1	soc-nv-flash
	on-board	Fixed partitions of a flash (or other non-volatile storage) memory1	fixed-partitions
Pin control	on-chip	LPC I/O Pin Configuration (IOCON)1	nxp,lpc-iocon
	on-chip	LPC pinctrl node1	nxp,lpc-iocon-pinctrl
PWM	on-chip	NXP SCTimer PWM1	nxp,sctimer-pwm
Reset controller	on-chip	LPC SYSCON Peripheral reset controller1	nxp,lpc-syscon-reset
RNG	on-chip	LPC RNG (Random Number Generator)1	nxp,lpc-rng
SDHC	on-chip	NXP LPC SDIF SD host controller1	nxp,lpc-sdif
Sensors	on-board	FXOS8700 6-axis accelerometer/magnetometer sensor1	nxp,fxos8700
Serial controller	on-chip	LPC USART2	nxp,lpc-usart
SPI	on-chip	NXP LPC SPI controller1	nxp,lpc-spi
SRAM	on-chip	Generic on-chip SRAM description6	mmio-sram
Timer	on-chip	ARMv8-M System Tick1	arm,armv8m-systick
USB	on-chip	NXP LPCIP3511 USB device mode2	nxp,lpcip3511
	on-chip	NXP USB high speed phy that is used on NXP RTxxxx, RTxxx, MCX, LPC and Kinetis platforms if high speed usb is supported on these platforms1	nxp,usbphy
Watchdog	on-chip	LPC Windowed Watchdog Timer1	nxp,lpc-wwdt

Targets available

The default configuration file boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_defconfig only enables the first core. CPU0 is the only target that can run standalone.

• lpcxpresso55s69/lpc55s69/cpu0 secure (S) address space for CPU0

• lpcxpresso55s69/lpc55s69/cpu0/ns non-secure (NS) address space for CPU0

• lpcxpresso55s69/lpc55s69/cpu1 CPU1 target, no security extensions

NS target for CPU0 does not work correctly without a secure image to configure the system, then hand execution over to the NS environment. To enable a secure image, run any of the tfm_integration samples. When using the NS target CONFIG_BUILD_WITH_TFM is always enabled to ensure that a valid S image is included during the build process.

CPU1 does not work without CPU0 enabling it. To enable it, run one of the following samples in subsys\ipc:

• ipm_mcux

• openamp

Connections and IOs

The LPC55S69 SoC has IOCON registers, which can be used to configure the functionality of a pin.

Name	Function	Usage
PIO0_26	SPI	SPI MOSI
PIO0_27	USART	USART TX
PIO0_29	USART	USART RX
PIO0_30	USART	USART TX
PIO1_1	SPI	SPI SSEL
PIO1_2	SPI	SPI SCK
PIO1_3	SPI	SPI MISO
PIO1_4	GPIO	RED LED
PIO1_6	GPIO	BLUE_LED
PIO1_7	GPIO	GREEN LED
PIO1_20	I2C	I2C SCL
PIO1_21	I2C	I2C SDA
PIO1_24	USART	USART RX
PIO0_20	I2S	I2S DATAOUT
PIO0_19	I2S	I2S TX WS
PIO0_21	I2S	I2S TX SCK
PIO1_13	I2S	I2S DATAIN
PIO0_15	SCT0_OUT2	PWM
PIO0_24	SD0_D0	SDHC
PIO0_25	SD0_D1	SDHC
PIO0_31	SD0_D2	SDHC
PIO0_7	SD0_CLK	SDHC
PIO0_8	SD0_CMD	SDHC
PIO0_9	SD0_POW_EN	SDHC
PIO1_0	SD0_D3	SDHC

Memory mappings

There are multiple memory configurations, they all start from the MCUboot partitioning which looks like the table below

Name	Address[Size]	Comment
boot	0x00000000[32K]	Bootloader
slot0	0x00008000[160k]	Image that runs after boot
slot0_ns	0x00030000[96k]	Second image, core 1 or NS
slot1	0x00048000[160k]	Updates slot0 image
slot1_ns	0x00070000[96k]	Updates slot0_ns image
storage	0x00088000[50k]	File system, persistent storage

See below examples of how this partitioning is used

Trusted Execution

Memory	Address[Size]	Comment
MCUboot	0x00000000[32K]	Secure bootloader
TFM_S	0x00008000[160k]	Secure image
Zephyr_NS	0x00030000[96k]	Non-Secure image
storage	0x00088000[50k]	Persistent storage

RAM	Address[Size]	Comment
secure_ram	0x20000000[136k]	Secure memory
non_secure_ram	0x20022000[136k]	Non-Secure memory

Dual Core samples

Memory	Address[Size]	Comment
CPU0	0x00000000[630K]	CPU0, can access all flash
CPU1	0x00030000[96k]	CPU1, has no MPU

RAM	Address[Size]	Comment
sram0	0x20000000[64k]	CPU0 memory
sram3	0x20030000[64k]	CPU1 memory
sram4	0x20040000[16k]	Mailbox/shared memory

System Clock

The LPC55S69 SoC is configured to use PLL1 clocked from the external 16MHz crystal, running at 144MHz as a source for the system clock. When the flash controller is enabled, the core clock will be reduced to 96MHz. The application may reconfigure clocks after initialization, provided that the core clock is always set to 96MHz when flash programming operations are performed.

Serial Port

The LPC55S69 SoC has 8 FLEXCOMM interfaces for serial communication. One is configured as USART for the console and the remaining are not used.

Programming and Debugging

Build and flash applications as usual (see Building an Application and Run an Application for more details).

Configuring a Debug Probe

LinkServer is the default runner for this board. A debug probe is used for both flashing and debugging the board. This board is configured by default to use the integrated MCU-Link Onboard Debug Probe in the CMSIS-DAP mode. To use this probe with Zephyr, you need to install the LinkServer Debug Host Tools and make sure they are in your search path. Refer to the detailed overview about Application Debugging for additional information.

The integrated MCU-Link hardware can also be used as a J-Link probe with a firmware update, as described in MCU-Link JLink Onboard Debug Probe. The J-Link Debug Host Tools should be available in this case.

Configuring a Console

Connect a USB cable from your PC to P6, and use the serial terminal of your choice (minicom, putty, etc.) with the following settings:

• Speed: 115200

• Data: 8 bits

• Parity: None

• Stop bits: 1

Flashing

Here is an example for the Hello World application. This example uses the LinkServer Debug Host Tools as default.

# From the root of the zephyr repository
west build -b lpcxpresso55s69/lpc55s69/cpu0 samples/hello_world
west flash

Open a serial terminal, reset the board (press the RESET button), and you should see the following message in the terminal:

***** Booting Zephyr OS v3.7.0 *****
Hello World! lpcxpresso55s69/lpc55s69/cpu0

Building and flashing secure/non-secure with Arm® TrustZone®

The TF-M integration samples can be run using the lpcxpresso55s69/lpc55s69/cpu0/ns target. To run we need to manually flash the resulting image (tfm_merged.hex) with a J-Link as follows (reset and erase are for recovering a locked core):

JLinkExe -device lpc55s69 -if swd -speed 2000 -autoconnect 1
J-Link>r
J-Link>erase
J-Link>loadfile build/zephyr/tfm_merged.hex

We need to reset the board manually after flashing the image to run this code.

Building a dual-core image

The dual-core samples are run using lpcxpresso55s69/lpc55s69/cpu0 target. Images built for lpcxpresso55s69/lpc55s69/cpu1 will be loaded from flash and executed on the second core when SECOND_CORE_MCUX is selected. For an example of building for both cores with sysbuild, see samples/subsys/ipc/openamp/

Debugging

Here is an example for the Hello World application. This example uses the J-Link Debug Host Tools as default.

# From the root of the zephyr repository
west build -b lpcxpresso55s69/lpc55s69/cpu0 samples/hello_world
west debug

Open a serial terminal, step through the application in your debugger, and you should see the following message in the terminal:

***** Booting Zephyr OS zephyr-v1.14.0 *****
Hello World! lpcxpresso55s69

Support Resources for Zephyr

• NXP Zephyr Downstream Software Development Kit

• MCUXpresso for VS Code, wiki documentation and Zephyr lab guides

• NXP Zephyr Knowledge Hub

• NXP’s Zephyr landing page (including training resources)

• NXP Support Community forum for Zephyr