FRDM_RW612

Board Overview

FRDM_RW612

Name:

frdm_rw612

Vendor:

NXP Semiconductors

Architecture:

arm

SoC:

rw612

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Overview

The RW612 is a highly integrated, low-power tri-radio wireless MCU with an integrated 260 MHz ARM Cortex-M33 MCU and Wi-Fi 6 + Bluetooth Low Energy (LE) 5.3 / 802.15.4 radios designed for a broad array of applications, including connected smart home devices, gaming controllers, enterprise and industrial automation, smart accessories and smart energy.

The RW612 MCU subsystem includes 1.2 MB of on-chip SRAM and a high-bandwidth Quad SPI interface with an on-the-fly decryption engine for securely accessing off-chip XIP flash.

The advanced design of the RW612 delivers tight integration, low power and highly secure operation in a space- and cost-efficient wireless MCU requiring only a single 3.3 V power supply.

Hardware

• 260 MHz ARM Cortex-M33, tri-radio cores for Wifi 6 + BLE 5.3 + 802.15.4

• 1.2 MB on-chip SRAM

Supported Features

The frdm_rw612 board supports the hardware features listed below.

on-chip / on-board

Feature integrated in the SoC / present on the board.

2 / 2

Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.

vnd,foo

Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

frdm_rw612

/

rw612

frdm_rw612/rw612 target

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-M33F CPU1	arm,cortex-m33f
ADC	on-chip	NXP GAU GPADC1 1	nxp,gau-adc
ARM architecture	on-chip	LPC Flexcomm node1	nxp,lpc-flexcomm
	on-chip	RW SOC controller node2	nxp,rw-soc-ctrl
	on-chip	NXP NBU interruption information1	nxp,nbu
Audio	on-chip	NXP DMIC1	nxp,dmic
Bluetooth	on-chip	NXP BLE HCI information1	nxp,hci-ble
Clock control	on-chip	LPC SYSCON & CLKCTL IP node2	nxp,lpc-syscon
Counter	on-chip	Driver that uses the NXP LPC RTC High resolution counter1	nxp,lpc-rtc-highres
	on-chip	NXP MCUX Standard Timer/Counter1 3	nxp,lpc-ctimer
	on-chip	NXP Multirate Timer2	nxp,mrt
	on-chip	NXP Multirate Timer Channel1 7	nxp,mrt-channel
DAC	on-chip	NXP GAU DAC1	nxp,gau-dac
DMA	on-chip	NXP LPC DMA controller1	nxp,lpc-dma
Ethernet	on-chip	NXP ENET IP Module1	nxp,enet
	on-chip	NXP ENET MAC/L2 Device1	nxp,enet-mac
	on-board	Microchip KSZ8081 Ethernet PHY device1	microchip,ksz8081
	on-chip	NXP ENET PTP (Precision Time Protocol) Clock1	nxp,enet-ptp-clock
GPIO & Headers	on-chip	LPC GPIO1	nxp,lpc-gpio
	on-chip	LPC GPIO port device2	nxp,lpc-gpio-port
	on-board	GPIO pins exposed on NXP LCD pmod interface (e.g., used on LCD-PAR-035 panel)1	nxp,lcd-pmod
IEEE 802.15.4 HDLC RCP interface	on-chip	NXP HDLC RCP interface node1	nxp,hdlc-rcp-if
I2C	on-chip	LPC I2C1	nxp,lpc-i2c
Input	on-board	Group of GPIO-bound input keys1	gpio-keys
Interrupt controller	on-chip	ARMv8-M NVIC (Nested Vectored Interrupt Controller)1	arm,v8m-nvic
	on-chip	NXP Pin interrupt and pattern match engine (PINT)1	nxp,pint
LED	on-board	Group of GPIO-controlled LEDs1	gpio-leds
MDIO	on-chip	NXP ENET MDIO Features1	nxp,enet-mdio
MIPI-DBI	on-chip	NXP LCDIC Controller1	nxp,lcdic
MMU / MPU	on-chip	ARMv8-M MPU (Memory Protection Unit)1	arm,armv8m-mpu
MTD	on-board	NXP FlexSPI NOR1	nxp,imx-flexspi-nor
	on-board	Fixed partitions of a flash (or other non-volatile storage) memory1	fixed-partitions
	on-board	AP Memory APS6404L pSRAM on NXP FlexSPI bus1	nxp,imx-flexspi-aps6404l
Pin control	on-chip	MCI IO MUX Pin Controller1	nxp,mci-io-mux
Power management	on-chip	NXP RW PMU1	nxp,rw-pmu
	on-chip	Some NXP SoC’s have pins dedicated to generate a wakeup interrupt2	nxp,aon-wakeup-pin
	on-chip	Properties for NXP power management through the PDCFG register1 1	nxp,pdcfg-power
Power domain	on-chip	This power domain will Turn On and Off devices when transitioning in and out a specified Power State1	power-domain-soc-state-change
PWM	on-chip	NXP SCTimer PWM1	nxp,sctimer-pwm
Reset controller	on-chip	NXP RSTCTL Peripheral reset controller2	nxp,rstctl
RNG	on-chip	Kinetis TRNG (True Random Number Generator)1	nxp,kinetis-trng
RTC	on-chip	NXP LPC RTC1	nxp,lpc-rtc
Serial controller	on-chip	LPC USART1 1	nxp,lpc-usart
SPI	on-chip	NXP FlexSPI controller1	nxp,imx-flexspi
	on-chip	NXP LPC SPI controller1	nxp,lpc-spi
SRAM	on-chip	Generic on-chip SRAM description2	mmio-sram
Timer	on-chip	ARMv8-M System Tick1	arm,armv8m-systick
	on-chip	NXP OS Timer on i.MX-RT5xx/6xx1	nxp,os-timer
USB	on-chip	NXP EHCI USB device mode1	nxp,ehci
Watchdog	on-chip	LPC Windowed Watchdog Timer1	nxp,lpc-wwdt

Programming and Debugging

Build and flash applications as usual (see Building an Application and Run an Application for more details).

Configuring a Debug Probe

A debug probe is used for both flashing and debugging the board. This board is configured by default to use the JLink Firmware.

Configuring a Console

Connect a USB cable from your PC to J10, and use the serial terminal of your choice (minicom, putty, etc.) with the following settings:

• Speed: 115200

• Data: 8 bits

• Parity: None

• Stop bits: 1

Flashing

Here is an example for the Hello World application. This example uses the J-Link Debug Host Tools as default.

# From the root of the zephyr repository
west build -b frdm_rw612 samples/hello_world
west flash

Open a serial terminal, reset the board (press the RESET button), and you should see the following message in the terminal:

***** Booting Zephyr OS v3.6.0 *****
Hello World! frdm_rw612

Debugging

Here is an example for the Hello World application. This example uses the J-Link Debug Host Tools as default.

# From the root of the zephyr repository
west build -b frdm_rw612 samples/hello_world
west debug

Open a serial terminal, step through the application in your debugger, and you should see the following message in the terminal:

***** Booting Zephyr OS zephyr-v3.6.0 *****
Hello World! frdm_rw612

SRAM Bus Access Partitioning

RW612 supports shared access of the SRAM from both the code bus and data bus. The bus used to access the SRAM is determined using two separate memory mapped address spaces. The application can configure the partitioning of the SRAM access regions by a devicetree overlay. For example, below is part of an overlay to change the whole SRAM to be used for data.

&sram_data {
     reg = <0x0 DT_SIZE_K(1216)>;
};

Wireless Connectivity Support

Fetch Binary Blobs

To support Bluetooth or Wi-Fi, frdm_rw612 requires fetching binary blobs, which can be achieved by running the following command:

west blobs fetch hal_nxp

Bluetooth

BLE functionality requires to fetch binary blobs, so make sure to follow the Fetch Binary Blobs section first.

frdm_rw612 platform supports the monolithic feature. The required binary blob <zephyr workspace>/modules/hal/nxp/zephyr/blobs/rw61x_sb_ble_a2.bin will be linked with the application image directly, forming one single monolithic image.

Wi-Fi

Wi-Fi functionality requires to fetch binary blobs, so make sure to follow the Fetch Binary Blobs section first.

frdm_rw612 platform supports the monolithic feature. The required binary blob <zephyr workspace>/modules/hal/nxp/zephyr/blobs/rw61x_sb_wifi_a2.bin will be linked with the application image directly, forming one single monolithic image.

Support Resources for Zephyr

• NXP Zephyr Downstream Software Development Kit

• MCUXpresso for VS Code, wiki documentation and Zephyr lab guides

• NXP Zephyr Knowledge Hub

• NXP’s Zephyr landing page (including training resources)

• NXP Support Community forum for Zephyr