i.MX8MM EVK

Board Overview

Name:

imx8mm_evk

Vendor:

NXP Semiconductors

Architecture:

arm, arm64

SoC:

mimx8mm6

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Overview

i.MX8M Mini LPDDR4 EVK board is based on NXP i.MX8M Mini applications processor, composed of a quad Cortex®-A53 cluster and a single Cortex®-M4 core. Zephyr OS is ported to run on the Cortex®-A53 core.

• Board features:

  • RAM: 2GB LPDDR4

  • Storage:

    • SanDisk 16GB eMMC5.1

    • Micron 32MB QSPI NOR

    • microSD Socket

  • Wireless:

    • WiFi: 2.4/5GHz IEEE 802.11b/g/n

    • Bluetooth: v4.1

  • USB:

    • OTG - 2x type C

  • Ethernet

  • PCI-E M.2

  • Connectors:

    • 40-Pin Dual Row Header

  • LEDs:

    • 1x Power status LED

    • 1x UART LED

  • Debug

    • JTAG 20-pin connector

    • MicroUSB for UART debug, two COM ports for A53 and M4

More information about the board can be found at the NXP website.

Supported Features

The imx8mm_evk board supports the hardware features listed below.

on-chip / on-board

Feature integrated in the SoC / present on the board.

2 / 2

Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.

vnd,foo

Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

imx8mm_evk

/

mimx8mm6/a53mimx8mm6/a53/smpmimx8mm6/m4

imx8mm_evk/mimx8mm6/a53 target

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-A53 CPU1 3	arm,cortex-a53
Clock control	on-chip	i.MX CCM (Clock Controller Module) IP node1	nxp,imx-ccm
Ethernet	on-chip	NXP ENET1G IP Module1	nxp,enet1g
	on-chip	NXP ENET MAC/L2 Device1	nxp,enet-mac
	on-board	Qualcomm Atheros AR8031 Ethernet PHY1	qca,ar8031
	on-chip	NXP ENET PTP (Precision Time Protocol) Clock1	nxp,enet-ptp-clock
GPIO & Headers	on-chip	i.MX GPIO1 4	nxp,imx-gpio
	on-board	PCA6416 I2C-based GPIO expander1	nxp,pca6416
I2C	on-chip	NXP II2C1 3	nxp,ii2c
Interrupt controller	on-chip	ARM Generic Interrupt Controller v31	arm,gic-v3
MDIO	on-chip	NXP ENET MDIO Features1	nxp,enet-mdio
Miscellaneous	on-chip	NXP i.MX Resource Domain Controller (RDC)1	nxp,rdc
Pin control	on-chip	This compatible binding should be applied to the device’s iomuxc DTS node1	nxp,imx-iomuxc
	on-chip	The node has the ‘pinctrl’ node label set in MCUX SoC’s devicetree1	nxp,imx8mp-pinctrl
Serial controller	on-chip	This binding gives a base representation of the NXP iMX IUART1 1	nxp,imx-iuart
Timer	on-chip	per-core ARM architected timer1	arm,armv8-timer
	on-chip	NXP MCUX General-Purpose Timer (GPT)2	nxp,imx-gpt

imx8mm_evk/mimx8mm6/a53/smp target

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-A53 CPU2 2	arm,cortex-a53
Clock control	on-chip	i.MX CCM (Clock Controller Module) IP node1	nxp,imx-ccm
Ethernet	on-chip	NXP ENET1G IP Module1	nxp,enet1g
	on-chip	NXP ENET MAC/L2 Device1	nxp,enet-mac
	on-board	Qualcomm Atheros AR8031 Ethernet PHY1	qca,ar8031
	on-chip	NXP ENET PTP (Precision Time Protocol) Clock1	nxp,enet-ptp-clock
GPIO & Headers	on-chip	i.MX GPIO5	nxp,imx-gpio
I2C	on-chip	NXP II2C4	nxp,ii2c
Interrupt controller	on-chip	ARM Generic Interrupt Controller v31	arm,gic-v3
MDIO	on-chip	NXP ENET MDIO Features1	nxp,enet-mdio
Miscellaneous	on-chip	NXP i.MX Resource Domain Controller (RDC)1	nxp,rdc
Pin control	on-chip	This compatible binding should be applied to the device’s iomuxc DTS node1	nxp,imx-iomuxc
	on-chip	The node has the ‘pinctrl’ node label set in MCUX SoC’s devicetree1	nxp,imx8mp-pinctrl
Power management CPU operations	on-board	Power State Coordination Interface (PSCI) version 0.21	arm,psci-0.2
Serial controller	on-chip	This binding gives a base representation of the NXP iMX IUART1 1	nxp,imx-iuart
Timer	on-chip	per-core ARM architected timer1	arm,armv8-timer
	on-chip	NXP MCUX General-Purpose Timer (GPT)2	nxp,imx-gpt

imx8mm_evk/mimx8mm6/m4 target

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-M4 CPU1	arm,cortex-m4
ARM architecture	on-chip	i.MX ITCM (Instruction Tightly Coupled Memory)1	nxp,imx-itcm
	on-chip	i.MX DTCM (Data Tightly Coupled Memory)1	nxp,imx-dtcm
Clock control	on-chip	i.MX CCM (Clock Controller Module) IP node1	nxp,imx-ccm
GPIO & Headers	on-chip	i.MX GPIO5	nxp,imx-gpio
Interrupt controller	on-chip	ARMv7-M NVIC (Nested Vectored Interrupt Controller)1	arm,v7m-nvic
IPM	on-chip	i.MX Messaging Unit1	nxp,imx-mu
Pin control	on-chip	This compatible binding should be applied to the device’s iomuxc DTS node1	nxp,imx-iomuxc
	on-chip	The node has the ‘pinctrl’ node label set in MCUX SoC’s devicetree1	nxp,imx8mp-pinctrl
Serial controller	on-chip	This binding gives a base representation of the NXP iMX IUART1 3	nxp,imx-iuart
SPI	on-chip	NXP i.MX ECSPI controller3	nxp,imx-ecspi
Timer	on-chip	ARMv7-M System Tick1	arm,armv7m-systick

Note

It is recommended to disable peripherals used by the M4 core on the Linux host.

Devices

System Clock

This board configuration uses a system clock frequency of 8 MHz.

The M4 Core is configured to run at a 400 MHz clock speed.

Serial Port

This board configuration uses a single serial communication channel with the CPU’s UART4. This is used for the M4 and A53 core targets.

Programming and Debugging (A53)

U-Boot “cpu” command is used to load and kick Zephyr to Cortex-A secondary Core, Currently it is supported in : Real-Time Edge U-Boot (use the branch “uboot_vxxxx.xx-y.y.y, xxxx.xx is uboot version and y.y.y is Real-Time Edge Software version, for example “uboot_v2023.04-2.9.0” branch is U-Boot v2023.04 used in Real-Time Edge Software release v2.9.0), and pre-build images and user guide can be found at Real-Time Edge Software.

Copy the compiled zephyr.bin to the first FAT partition of the SD card and plug the SD card into the board. Power it up and stop the u-boot execution at prompt.

Use U-Boot to load and kick zephyr.bin to Cortex-A53 Core0:

fatload mmc 1:1 0x93c00000 zephyr.bin; dcache flush; icache flush; go 0x93c00000

Or kick zephyr.bin to the other Cortex-A53 Core, for example Core2:

fatload mmc 1:1 0x93c00000 zephyr.bin; dcache flush; icache flush; cpu 2 release 0x93c00000

Use this configuration to run basic Zephyr applications and kernel tests, for example, with the Basic Synchronization sample:

# From the root of the zephyr repository
west build -b imx8mm_evk/mimx8mm6/a53 samples/synchronization
west build -t run

This will build an image with the synchronization sample app, boot it and display the following ram console output:

*** Booting Zephyr OS build zephyr-v3.1.0-3575-g44dd713bd883  ***
thread_a: Hello World from cpu 0 on mimx8mm_evk_a53!
thread_b: Hello World from cpu 0 on mimx8mm_evk_a53!
thread_a: Hello World from cpu 0 on mimx8mm_evk_a53!
thread_b: Hello World from cpu 0 on mimx8mm_evk_a53!
thread_a: Hello World from cpu 0 on mimx8mm_evk_a53!

Use Jailhouse hypervisor, after root cell linux is up:

#jailhouse enable imx8mm.cell
#jailhouse cell create imx8mm-zephyr.cell
#jailhouse cell load 1 zephyr.bin -a 0x93c00000
#jailhouse cell start 1

Programming and Debugging (M4)

The MIMX8MM EVK board doesn’t have QSPI flash for the M4 and it needs to be started by the A53 core. The A53 core is responsible to load the M4 binary application into the RAM, put the M4 in reset, set the M4 Program Counter and Stack Pointer, and get the M4 out of reset. The A53 can perform these steps at bootloader level or after the Linux system has booted.

The M4 can use up to 3 different RAMs. These are the memory mapping for A53 and M4:

Region	Cortex-A53	Cortex-M4 (System Bus)	Cortex-M4 (Code Bus)	Size
OCRAM	0x00900000-0x0093FFFF	0x20200000-0x2023FFFF	0x00900000-0x0093FFFF	256KB
TCMU	0x00800000-0x0081FFFF	0x20000000-0x2001FFFF		128KB
TCML	0x007E0000-0x007FFFFF		0x1FFE0000-0x1FFFFFFF	128KB
OCRAM_S	0x00180000-0x00187FFF	0x20180000-0x20187FFF	0x00180000-0x00187FFF	32KB

For more information about memory mapping see the i.MX 8M Applications Processor Reference Manual (section 2.1.2 and 2.1.3)

At compilation time you have to choose which RAM will be used. This configuration is done in the file boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_m4.dts with “zephyr,flash” (when CONFIG_XIP=y) and “zephyr,sram” properties. The available configurations are:

"zephyr,flash"
- &tcml_code
- &ocram_code
- &ocram_s_code

"zephyr,sram"
- &tcmu_sys
- &ocram_sys
- &ocram_s_sys

Load and run Zephyr on M4 from A53 using u-boot by copying the compiled zephyr.bin to the first FAT partition of the SD card and plug the SD card into the board. Power it up and stop the u-boot execution at prompt.

Load the M4 binary onto the desired memory and start its execution using:

fatload mmc 0:1 0x7e0000 zephyr.bin;bootaux 0x7e0000

Debugging

MIMX8MM EVK board can be debugged by connecting an external JLink JTAG debugger to the J902 debug connector and to the PC. Then the application can be debugged using the usual way.

Here is an example for the Hello World application.

# From the root of the zephyr repository
west build -b imx8mm_evk/mimx8mm6/m4 samples/hello_world
west debug

Open a serial terminal, step through the application in your debugger, and you should see the following message in the terminal:

***** Booting Zephyr OS build zephyr-v2.0.0-1859-g292afe8533c0 *****
Hello World! imx8mm_evk

Support Resources for Zephyr

• NXP Zephyr Downstream Software Development Kit

• MCUXpresso for VS Code, wiki documentation and Zephyr lab guides

• NXP Zephyr Knowledge Hub

• NXP’s Zephyr landing page (including training resources)

• NXP Support Community forum for Zephyr