MIMXRT1010-EVK

Overview

The i.MX RT1010 offer a new entry-point into the i.MX RT crossover processor series by providing the lowest-cost LQFP package option, combined with the high performance and ease-of-use known throughout the entire i.MX RT series. This device is fully supported by NXP’s MCUXpresso Software and Tools.

Hardware

  • MIMXRT1011DAE5A MCU

  • Memory

    • 128 Mbit QSPI Flash

  • Connectivity

    • Micro USB host and OTG connectors

    • Arduino interface

  • Audio

    • Audio Codec

    • 4-pole audio headphone jack

    • External speaker connection

    • Microphone

  • Debug

    • JTAG 10-pin connector

    • OpenSDA with DAPLink

For more information about the MIMXRT1010 SoC and MIMXRT1010-EVK board, see these references:

External Memory

This platform has the following external memories:

Device

Controller

Status

AT25SF128A

FLEXSPI

Enabled via flash configuration block, which sets up FLEXSPI at boot time.

Supported Features

The mimxrt1010_evk board supports the hardware features listed below.

on-chip / on-board
Feature integrated in the SoC / present on the board.
2 / 2
Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.
vnd,foo
Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.
mimxrt1010_evk
/
mimxrt1011

Type

Location

Description

Compatible

CPU

on-chip

ARM Cortex-M7 CPU1

arm,cortex-m7

ADC

on-chip

NXP MCUA 12B1MSPS SAR ADC1 1

nxp,mcux-12b1msps-sar

ARM architecture

on-chip

MCUX XBAR (Crossbar)3

nxp,mcux-xbar

Clock control

on-chip

i.MX CCM (Clock Controller Module) IP node1

nxp,imx-ccm

on-chip

Generic fixed factor clock provider2

fixed-factor-clock

on-chip

i.MX CCM Fractional PLL1

nxp,imx-ccm-fnpll

on-chip

i.MX ANATOP (Analog Clock Controller Module) IP node1

nxp,imx-anatop

on-chip

Generic fixed-rate clock provider4

fixed-clock

Counter

on-chip

NXP Periodic Interrupt Timer (PIT)1

nxp,pit

on-chip

Child node for the Periodic Interrupt Timer node, intended for an individual timer channel4

nxp,pit-channel

Cryptographic accelerator

on-chip

NXP Data Co-Processor (DCP) Crypto accelerator1

nxp,mcux-dcp

Debug

on-chip

ARMv7 instrumentation trace macrocell1

arm,armv7m-itm

DMA

on-chip

NXP MCUX EDMA controller1

nxp,mcux-edma

on-chip

NXP PXP 2D DMA engine1

nxp,pxp

GPIO & Headers

on-chip

i.MX GPIO3

nxp,imx-gpio

on-board

GPIO pins exposed on Arduino Uno (R3) headers1

arduino-header-r3

I2C

on-chip

NXP LPI2C controller1 1

nxp,lpi2c

I2S

on-chip

NXP mcux SAI-I2S controller2

nxp,mcux-i2s

Input

on-board

Group of GPIO-bound input keys1

gpio-keys

Interrupt controller

on-chip

ARMv7-M NVIC (Nested Vectored Interrupt Controller)1

arm,v7m-nvic

LED

on-board

Group of GPIO-controlled LEDs1

gpio-leds

Memory controller

on-chip

NXP FlexRAM on-chip ram controller If the flexram,bank-spec property is specified, then the flexram will be dynamically reconfigured to the configuration specified at runtime1

nxp,flexram

Miscellaneous

on-chip

NXP FlexIO controller1

nxp,flexio

MMU / MPU

on-chip

ARMv7-M Memory Protection Unit (MPU)1

arm,armv7m-mpu

MTD

on-board

NXP FlexSPI NOR1

nxp,imx-flexspi-nor

on-board

Fixed partitions of a flash (or other non-volatile storage) memory1

fixed-partitions

Pin control

on-chip

This compatible binding should be applied to the device’s iomuxc DTS node1

nxp,imx-iomuxc

on-chip

The node has the ‘pinctrl’ node label set in MCUX RT SoC’s devicetree1

nxp,mcux-rt-pinctrl

on-chip

i.MX IOMUXC1

nxp,imx-gpr

PWM

on-chip

NXP eFLEX PWM module with mcux-pwm submodules1

nxp,flexpwm

on-chip

NXP MCUX PWM4

nxp,imx-pwm

RNG

on-chip

Kinetis TRNG (True Random Number Generator)1

nxp,kinetis-trng

RTC

on-chip

NXP SNVS LP/HP RTC1

nxp,imx-snvs-rtc

Sensors

on-chip

NXP MCUX QDEC4

nxp,mcux-qdec

on-chip

NXP on-die temperature monitor1

nxp,tempmon

Serial controller

on-chip

NXP LPUART1 3

nxp,lpuart

SPI

on-chip

NXP FlexSPI controller1

nxp,imx-flexspi

on-chip

NXP LPSPI controller1 1

nxp,lpspi

Timer

on-chip

ARMv7-M System Tick1

arm,armv7m-systick

on-chip

NXP MCUX General-Purpose HW Timer (GPT)1

nxp,gpt-hw-timer

on-chip

NXP MCUX General-Purpose Timer (GPT)1

nxp,imx-gpt

USB

on-chip

NXP USB high speed phy that is used on NXP RTxxxx, RTxxx, MCX, LPC and Kinetis platforms if high speed usb is supported on these platforms2

nxp,usbphy

on-chip

NXP EHCI USB device mode1

nxp,ehci

Watchdog

on-chip

imxRT watchdog1

nxp,imx-wdog

Note

For additional features not yet supported, please also refer to the MIMXRT1064-EVK, which is the superset board in NXP’s i.MX RT10xx family. NXP prioritizes enabling the superset board with NXP’s Full Platform Support for Zephyr. Therefore, the mimxrt1064_evk board may have additional features already supported, which can also be re-used on this mimxrt1010_evk board:

Connections and I/Os

The MIMXRT1010 SoC has five pairs of pinmux/gpio controllers.

Name

Function

Usage

GPIO_11

GPIO

LED

GPIO_SD_05

GPIO

SW4

GPIO_10

LPUART1_TX

UART Console

GPIO_09

LPUART1_RX

UART Console

GPIO_01

LPI2C1_SDA

I2C SDA

GPIO_02

LPI2C1_CLK

I2C SCL

GPIO_AD_03

LPSPI1_SDI

SPI

GPIO_AD_04

LPSPI1_SDO

SPI

GPIO_AD_05

LPSPI1_PCS0

SPI

GPIO_AD_06

LPSPI1_SCK

SPI

GPIO_AD_01

ADC

ADC1 Channel 1

GPIO_AD_02

ADC

ADC1 Channel 2

System Clock

The MIMXRT1010 SoC is configured to use SysTick as the system clock source, running at 500MHz.

When power management is enabled, the 32 KHz low frequency oscillator on the board will be used as a source for the GPT timer to generate a system clock. This clock enables lower power states, at the cost of reduced resolution

Serial Port

The MIMXRT1010 SoC has four UARTs. LPUART1 is configured for the console, and the remaining are not used.

Programming and Debugging

This board supports 3 debug host tools. Please install your preferred host tool, then follow the instructions in Configuring a Debug Probe to configure the board appropriately.

Once the host tool and board are configured, build and flash applications as usual (see Building an Application and Run an Application for more details).

Configuring a Debug Probe

For the RT1010, J61/J62 are the SWD isolation jumpers, J22 is the DFU mode jumper, and J16 is the 10 pin JTAG/SWD header.

A debug probe is used for both flashing and debugging the board. This board has an LPC-LINK2 Onboard Debug Probe. The default firmware present on this probe is the LPC-Link2 DAPLink Onboard Debug Probe.

Based on the host tool installed, please use the following instructions to setup your debug probe:

Using CMSIS-DAP with LPC-Link2 Probe

  1. Follow the instructions provided at LPC-LINK2 CMSIS DAP Onboard Debug Probe to reprogram the default debug probe firmware on this board.

  2. Ensure the SWD isolation jumpers are populated

Configuring a Console

Regardless of your choice in debug probe, we will use the OpenSDA microcontroller as a usb-to-serial adapter for the serial console. Check that jumpers J31 and J32 are on (they are on by default when boards ship from the factory) to connect UART signals to the OpenSDA microcontroller.

Connect a USB cable from your PC to J41.

Use the following settings with your serial terminal of choice (minicom, putty, etc.):

  • Speed: 115200

  • Data: 8 bits

  • Parity: None

  • Stop bits: 1

Flashing

Here is an example for the Hello World application.

# From the root of the zephyr repository
west build -b mimxrt1010_evk samples/hello_world
west flash

Open a serial terminal, reset the board (press the SW9 button), and you should see the following message in the terminal:

Hello World! mimxrt1010_evk

Support Resources for Zephyr