i.MX91 EVK

Overview

The i.MX 91 Evaluation Kit (MCIMX91-EVK board) is a platform designed to display the most commonly used features of the i.MX 91 applications processor. The MCIMX91-EVK board is an entry-level development board with a small and low-cost package. The board can be used by developers to get familiar with the processor before investing a large amount of resources in more specific designs.

The i.MX 91 applications processor features an Arm Cortex-A55 core that can operate at speeds of up to 1.4 GHz.

  • Board features:

    • RAM: 2GB LPDDR4

    • Storage:

      • SanDisk 16GB eMMC5.1

      • microSD Socket

    • Wireless:

      • Murata Type-2EL (SDIO+UART+SPI) module. It is based on NXP IW612 SoC, which supports dual-band (2.4 GHz /5 GHz) 1x1 Wi-Fi 6, Bluetooth 5.2, and 802.15.4

    • USB:

      • Two USB 2.0 Type C connectors

    • Ethernet:

      • ENET: 10/100/1000 Mbit/s RGMII Ethernet connected with external PHY RTL8211

      • ENET_QoS: 10/100/1000 Mbit/s RGMII Ethernet supporting TSN connected with external PHY RTL8211

    • PCIe:

      • One M.2/NGFF Key E mini card 75-pin connector

    • Connectors:

      • 40-Pin Dual Row Header

    • LEDs:

      • 1x Power status LED

      • 2x UART LED

    • Debug:

      • JTAG 20-pin connector

      • MicroUSB for UART debug

Supported Features

The imx91_evk board supports the hardware features listed below.

on-chip / on-board
Feature integrated in the SoC / present on the board.
2 / 2
Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.
vnd,foo
Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.
imx91_evk
/
mimx9131

Type

Location

Description

Compatible

CPU

on-chip

ARM Cortex-A55 CPU1

arm,cortex-a55

Clock control

on-chip

i.MX CCM Rev2 (Clock Controller Module) IP node1

nxp,imx-ccm-rev2

Interrupt controller

on-chip

ARM Generic Interrupt Controller v31

arm,gic-v3

Pin control

on-chip

This compatible binding should be applied to the device’s iomuxc DTS node1

nxp,imx-iomuxc

on-chip

The node has the ‘pinctrl’ node label set in MCUX SoC’s devicetree1

nxp,imx93-pinctrl

Power management CPU operations

on-chip

Power State Coordination Interface (PSCI) version 1.11

arm,psci-1.1

Serial controller

on-chip

NXP LPUART1 1

nxp,lpuart

Timer

on-chip

per-core ARM architected timer1

arm,armv8-timer

Devices

System Clock

This board configuration uses a system clock frequency of 24 MHz. Cortex-A55 Core runs up to 1.4 GHz.

Serial Port

This board configuration uses a single serial communication channel with the CPU’s UART1 for A55 core.

Programming and Debugging

U-Boot “go” command is used to load and kick Zephyr to Cortex-A55 Core.

Copy the compiled zephyr.bin to the first FAT partition of the SD card and plug the SD card into the board. Power it up and stop the u-boot execution at prompt.

Use U-Boot to load and kick zephyr.bin to Cortex-A55 Core:

fatload mmc 1:1 0x80000000 zephyr.bin; dcache flush; icache flush; go 0x80000000

Use this configuration to run basic Zephyr applications and kernel tests, for example, with the Basic Synchronization sample:

# From the root of the zephyr repository
west build -b imx91_evk/mimx9131 samples/synchronization

This will build an image with the synchronization sample app, boot it and display the following console output:

*** Booting Zephyr OS build v4.0.0-3277-g69f43115c9a8 ***
thread_a: Hello World from cpu 0 on imx91_evk!
thread_b: Hello World from cpu 0 on imx91_evk!
thread_a: Hello World from cpu 0 on imx91_evk!
thread_b: Hello World from cpu 0 on imx91_evk!

Support Resources for Zephyr