MIMXRT1180-EVK
Overview
The dual core i.MX RT1180 runs on the Cortex-M33 core at 240 MHz and on the Cortex-M7 at 792 MHz. The i.MX RT1180 MCU offers support over a wide temperature range and is qualified for consumer, industrial and automotive markets.
Hardware
MIMXRT1189CVM8B MCU
240MHz Cortex-M33 & 792Mhz Cortex-M7
1.5MB SRAM with 512KB of TCM for Cortex-M7 and 256KB of TCM for Cortex-M4
Memory
512 Mbit SDRAM
128 Mbit QSPI Flash
512 Mbit HYPER RAM
TF socket for SD card
Ethernet
1000 Mbit/s Ethernet PHY
USB
2* USB 2.0 OTG connector
Audio
3.5 mm audio stereo headphone jack
Board-mounted microphone
Left and right speaker out connectors
Power
5 V DC jack
Debug
JTAG 20-pin connector
MCU-Link with DAPLink
Expansion port
Arduino interface
CAN bus connector
For more information about the MIMXRT1180 SoC and MIMXRT1180-EVK board, see these references:
External Memory
This platform has the following external memories:
Device |
Controller |
Status |
|---|---|---|
W9825G6KH |
SEMC |
Enabled via device configuration data block, which sets up SEMC at boot time |
W25Q128JWSIQ |
FLEXSPI |
Enabled via flash configuration block, which sets up FLEXSPI at boot time. |
Supported Features
NXP considers the MIMXRT1180-EVK as the superset board for the i.MX RT118x family of MCUs. This board is a focus for NXP’s Full Platform Support for Zephyr, to better enable the entire RT118x family. NXP prioritizes enabling this board with new support for Zephyr features.
The mimxrt1180_evk board supports the hardware features listed below.
- on-chip / on-board
- Feature integrated in the SoC / present on the board.
- 2 / 2
-
Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files. -
vnd,foo -
Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.
Type |
Location |
Description |
Compatible |
|---|---|---|---|
CPU |
on-chip |
ARM Cortex-M33F CPU1 |
|
ADC |
on-chip |
||
CAN |
on-chip |
||
Clock control |
on-chip |
i.MX CCM Rev2 (Clock Controller Module) IP node1 |
|
on-chip |
Generic fixed-rate clock provider2 |
||
Comparator |
on-chip |
NXP Kinetis ACMP (Analog CoMParator)4 |
|
Counter |
on-chip |
NXP MCUX Quad Timer (QTMR)8 |
|
on-chip |
NXP MCUX Quad Timer Channel32 |
||
on-chip |
|||
DMA |
on-chip |
NXP MCUX EDMA controller2 |
|
DSA |
on-chip |
NXP NETC ethernet switch1 |
|
Ethernet |
on-chip |
NXP i.MX NETC Physical Station Interface (PSI)2 |
|
on-board |
Generic MII PHY2 |
||
on-board |
Realtek RTL8211F Ethernet PHY device3 |
||
GPIO & Headers |
on-chip |
i.MX RGPIO6 |
|
I2C |
on-chip |
NXP LPI2C controller6 |
|
I3C |
on-chip |
||
Input |
on-board |
Group of GPIO-bound input keys1 |
|
Interrupt controller |
on-chip |
ARMv8-M NVIC (Nested Vectored Interrupt Controller)1 |
|
LED |
on-board |
Group of GPIO-controlled LEDs1 |
|
on-board |
Group of PWM-controlled LEDs1 |
||
Mailbox |
on-chip |
NXP i.MX Message Unit as Zephyr MBOX2 |
|
MDIO |
on-chip |
NXP i.MX NETC External MDIO controller1 |
|
MMU / MPU |
on-chip |
ARMv8-M MPU (Memory Protection Unit)1 |
|
MTD |
on-board |
NXP FlexSPI NOR1 |
|
on-board |
Fixed partitions of a flash (or other non-volatile storage) memory1 |
||
Pin control |
on-chip |
This compatible binding should be applied to the device’s iomuxc DTS node1 |
|
on-chip |
The node has the ‘pinctrl’ node label set in MCUX RT SoC’s devicetree1 |
||
on-chip |
The node has the ‘pinctrl’ node label set in MCUX RT SoC’s devicetree1 |
||
PWM |
on-chip |
NXP eFLEX PWM module with mcux-pwm submodules4 |
|
on-chip |
|||
on-chip |
MCUX Timer/PWM Module (TPM)6 |
||
SDHC |
on-chip |
||
Serial controller |
on-chip |
||
SPI |
on-chip |
||
on-chip |
|||
Timer |
on-chip |
ARMv8-M System Tick1 |
|
on-chip |
|||
USB |
on-chip |
NXP EHCI USB device mode2 |
|
on-chip |
NXP USB high speed phy that is used on NXP RTxxxx, RTxxx, MCX, LPC and Kinetis platforms if high speed usb is supported on these platforms2 |
||
Watchdog |
on-chip |
Connections and I/Os
The MIMXRT1180 SoC has six pairs of pinmux/gpio controllers.
Name |
Function |
Usage |
|---|---|---|
GPIO_AON_04 |
GPIO |
SW8 |
GPIO_AD_27 |
GPIO |
LED |
GPIO_AON_08 |
LPUART1_TX |
UART Console M33 core |
GPIO_AON_09 |
LPUART1_RX | UART Console M33 core |
|
GPIO_AON_19 |
LPUART12_TX | UART Console M7 core |
|
GPIO_AON_20 |
LPUART12_RX |
UART Console M7 core |
GPIO_SD_B1_00 |
SPI1_CS0 | spi |
|
GPIO_SD_B1_01 |
SPI1_CLK | spi |
|
GPIO_SD_B1_02 |
SPI1_SDO | spi |
|
GPIO_SD_B1_03 |
SPI1_SDI | spi |
|
UART for M7 core is connected to USB-to-UART J60 connector. Or user can use open JP7 Jumper to enable second UART on MCU LINK J53 connector.
System Clock
The MIMXRT1180 SoC is configured to use SysTick as the system clock source, running at 240MHz. When targeting the M7 core, SysTick will also be used, running at 792MHz
Serial Port
The MIMXRT1180 SoC has 12 UARTs. LPUART1 is configured for the CM33 console, the LPUART12 is configured for the CM7 console core and the remaining are not used.
Ethernet
NETC Ethernet driver supports to manage the Physical Station Interface (PSI). NETC DSA driver supports to manage switch ports. Current DSA support is with limitation that only switch function is available without management via DSA master port. DSA master port support is TODO work.
+--------+ +--------+
| ENETC1 | | ENETC0 |
| | | |
| Pseudo | | 1G |
| MAC | | MAC |
+--------+ +--------+
| zero copy interface |
+-------------- +--------+----------------+ |
| | Pseudo | | |
| | MAC | | |
| | | | |
| | Port 4 | | |
| +--------+ | |
| SWITCH CORE | |
+--------+ +--------+ +--------+ +--------+ |
| Port 0 | | Port 1 | | Port 2 | | Port 3 | |
| | | | | | | | |
| 1G | | 1G | | 1G | | 1G | |
| MAC | | MAC | | MAC | | MAC | |
+--------+-+--------+-+--------+-+--------+ |
| | | | |
NETC External Interfaces (4 switch ports, 1 end-point port)
Programming and Debugging
Build and flash applications as usual (see Building an Application and Run an Application for more details).
Configuring a Debug Probe
LinkServer is the default runner for this board. A debug probe is used for both flashing and debugging the board. This board is configured by default to use the MCU-Link CMSIS-DAP Onboard Debug Probe. The pyOCD Debug Host Tools do not yet support programming the external flashes on this board. Use one of the other supported debug probes below.
Using J-Link
Please ensure to use a version of JLINK above V7.94g and jumper JP5 is installed if using external jlink plus on J37 as debugger.
When debugging cm33 core, need to ensure the SW5 on “0100” mode. When debugging cm7 core, need to ensure the SW5 on “0001” mode. (Only support run cm7 image when debugging due to default boot core on board is cm33 core)
Install the J-Link Debug Host Tools and make sure they are in your search path.
There are two options: the onboard debug circuit can be updated with Segger J-Link firmware, or J-Link External Debug Probe can be attached to the EVK.
Using Linkserver
Please ensure to use a version of Linkserver above V1.5.30 and jumper JP5 is uninstalled (default setting).
When debugging cm33 core, need to ensure the SW5 on “0100” mode. When debugging cm7 core, need to ensure the SW5 on “0001” mode. (Only support run cm7 image when debugging due to default boot core on board is cm33 core)
Dual Core samples Debugging
When debugging dual core samples, need to ensure the SW5 on “0100” mode. The CM33 core is responsible for copying and starting the CM7. To debug the CM7 it is useful to put infinite while loop either in reset vector or into main function and attach via debugger to CM7 core.
CM7 core can be started again only after reset, so after flashing ensure to reset board.
Configuring a Console
Regardless of your choice in debug probe, we will use the MCU-Link microcontroller as a usb-to-serial adapter for the serial console. Check that jumpers JP5 and JP3 are on (they are on by default when boards ship from the factory) to connect UART signals to the MCU-Link microcontroller.
Connect a USB cable from your PC to J53.
Use the following settings with your serial terminal of choice (minicom, putty, etc.):
Speed: 115200
Data: 8 bits
Parity: None
Stop bits: 1
Flashing
Here is an example for the Hello World application on cm33 core.
Before power on the board, make sure SW5 is set to 0100b
# From the root of the zephyr repository
west build -b mimxrt1180_evk/mimxrt1189/cm33 samples/hello_world
west flash
Power off the board, then power on the board and open a serial terminal, reset the board (press the SW3 button), and you should see the following message in the terminal:
***** Booting Zephyr OS v3.7.0-xxx-xxxxxxxxxxxxx *****
Hello World! mimxrt1180_evk/mimxrt1189/cm33
Debugging
Here is an example for the Hello World application.
# From the root of the zephyr repository
west build -b mimxrt1180_evk/mimxrt1189/cm33 samples/hello_world
west debug
Open a serial terminal, step through the application in your debugger, and you should see the following message in the terminal:
***** Booting Zephyr OS v3.7.0-xxx-xxxxxxxxxxxxx *****
Hello World! mimxrt1180_evk/mimxrt1189/cm33
Support Resources for Zephyr
MCUXpresso for VS Code, wiki documentation and Zephyr lab guides
NXP’s Zephyr landing page (including training resources)