MIMXRT595-EVK

Board Overview

MIMXRT595-EVK

Name:

mimxrt595_evk

Vendor:

NXP Semiconductors

Architecture:

arm, xtensa

SoC:

mimxrt595s

Browse board sources

Overview

i.MX RT500 crossover MCUs are part of the edge computing family and are optimized for low-power HMI applications by combining a graphics engine and a streamlined Cadence Tensilica Fusion F1 DSP core with a next-generation Arm Cortex-M33 core. These devices are designed to unlock the potential of display-based applications with a secure, power-optimized embedded processor.

i.MX RT500 MCUs provides up to 5MB of on-chip SRAM and several high-bandwidth interfaces to access off-chip flash, including an Octal/Quad SPI interface with an on-the-fly decryption engine.

Hardware

• MIMXRT595SFFOC Cortex-M33 (275 MHz) core processor with Cadence Tensilica Fusion F1 DSP

• Onboard, high-speed USB, Link2 debug probe with CMSIS-DAP protocol (supporting Cortex M33 debug only)

• USB2.0 high-speed host and device with micro USB connector and external crystal

• Octal/Quad/pSRAM external memories via FlexSPI

• 5 MB system SRAM

• Full size SD card slot (SDIO)

• On-board eMMC chip

• On-board 5 V inputs NXP PCA9420UK PMIC providing 1.2 V, 1.8 V, 3.3 V

• User LEDs

• Reset and User buttons

• MIPI-DSI connector

• Single row headers for ARDUINO signals and MikroBus connector

• FlexIO connector for MikroElektronica TFT Proto 5 inch capacitive touch display

• One motion sensor combo accelero-/magneto-meter NXP FXOS8700CQ

• Stereo audio codec with line-In/ line-Out/ and Microphone

• Pmod/host expansion connector

• NXP TFA9896 audio digital amplifier

• Support for up to eight off-board digital microphones via 12-pin header

• Two on-board digital microphones

For more information about the MIMXRT595 SoC and MIMXRT595-EVK board, see these references:

• i.MX RT595 Website

• i.MX RT595 Datasheet

• i.MX RT595 Reference Manual

• MIMXRT595-EVK Website

• MIMXRT595-EVK User Guide

• MIMXRT595-EVK Schematics

• MIMXRT595-EVK Debug Firmware

Supported Features

NXP considers the MIMXRT595-EVK as a superset board for the i.MX RT5xx family of MCUs. This board is a focus for NXP’s Full Platform Support for Zephyr, to better enable the entire RT5xx family. NXP prioritizes enabling this board with new support for Zephyr features. Another very similar board is the MIMXRT685-EVK, and that board may have additional features already supported, which can also be re-used on this mimxrt595_evk board.

The mimxrt595_evk board supports the hardware features listed below.

on-chip / on-board

Feature integrated in the SoC / present on the board.

2 / 2

Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.

vnd,foo

Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

mimxrt595_evk

/

mimxrt595s/cm33

mimxrt595_evk/mimxrt595s/cm33 target

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-M33F CPU1	arm,cortex-m33f
ADC	on-chip	LPC LPADC1	nxp,lpc-lpadc
ARM architecture	on-chip	LPC Flexcomm node9	nxp,lpc-flexcomm
Audio	on-chip	NXP DMIC1	nxp,dmic
	on-board	WM8904 audio codec1	wolfson,wm8904
Clock control	on-chip	LPC SYSCON & CLKCTL IP node2	nxp,lpc-syscon
Counter	on-chip	Driver that uses the NXP LPC RTC High resolution counter1	nxp,lpc-rtc-highres
	on-chip	NXP MCUX Standard Timer/Counter5	nxp,lpc-ctimer
	on-chip	NXP Multirate Timer1	nxp,mrt
	on-chip	NXP Multirate Timer Channel1 3	nxp,mrt-channel
Display	on-chip	NXP DCNano LCDIF (LCD Interface) controller1	nxp,dcnano-lcdif
DMA	on-chip	NXP LPC DMA controller1 1	nxp,lpc-dma
	on-chip	NXP SmartDMA controller1	nxp,smartdma
GPIO & Headers	on-chip	LPC GPIO1	nxp,lpc-gpio
	on-chip	LPC GPIO port device7	nxp,lpc-gpio-port
	on-board	GPIO pins exposed on Arduino Uno (R3) headers1	arduino-header-r3
Hardware information	on-chip	NXP LPC 128-bit Unique identifier1	nxp,lpc-uid
I2C	on-chip	LPC I2C2	nxp,lpc-i2c
I2S	on-chip	LPC I2S node2	nxp,lpc-i2s
I3C	on-chip	NXP MCUX I3C controller1	nxp,mcux-i3c
Input	on-board	Group of GPIO-bound input keys1	gpio-keys
Interrupt controller	on-chip	NXP Pin interrupt and pattern match engine (PINT)1	nxp,pint
	on-chip	ARMv8-M NVIC (Nested Vectored Interrupt Controller)1	arm,v8m-nvic
LED	on-board	Group of GPIO-controlled LEDs1	gpio-leds
Mailbox	on-chip	NXP i.MX Message Unit as Zephyr MBOX1	nxp,mbox-imx-mu
MIPI-DSI	on-chip	NXP MCUX MIPI DSI 2L1	nxp,mipi-dsi-2l
MMU / MPU	on-chip	ARMv8-M MPU (Memory Protection Unit)1	arm,armv8m-mpu
MTD	on-board	NXP FlexSPI MX25UM51345G1	nxp,imx-flexspi-mx25um51345g
	on-board	Fixed partitions of a flash (or other non-volatile storage) memory1	fixed-partitions
	on-board	AP Memory APS6408L pSRAM on NXP FlexSPI bus1	nxp,imx-flexspi-aps6408l
Pin control	on-chip	LPC I/O Pin Configuration (IOCON)1	nxp,lpc-iocon
	on-chip	RT600/RT500 Pin Controller1	nxp,rt-iocon-pinctrl
Power management	on-chip	Properties for NXP power management through the PDCFG register1	nxp,pdcfg-power
PWM	on-chip	NXP SCTimer PWM1	nxp,sctimer-pwm
Regulator	on-board	NXP PCA9420 PMIC1	nxp,pca9420
	on-board	Fixed voltage regulators1	regulator-fixed
Reset controller	on-chip	NXP RSTCTL Peripheral reset controller2	nxp,rstctl
RNG	on-chip	Kinetis TRNG (True Random Number Generator)1	nxp,kinetis-trng
RTC	on-chip	NXP LPC RTC1	nxp,lpc-rtc
SDHC	on-chip	NXP imx USDHC controller1 1	nxp,imx-usdhc
Sensors	on-board	FXOS8700 6-axis accelerometer/magnetometer sensor1	nxp,fxos8700
Serial controller	on-chip	LPC USART2	nxp,lpc-usart
SPI	on-chip	NXP FlexSPI controller2	nxp,imx-flexspi
	on-chip	NXP LPC SPI controller1 1	nxp,lpc-spi
SRAM	on-chip	Generic on-chip SRAM description2	mmio-sram
Timer	on-chip	NXP OS Timer on i.MX-RT5xx/6xx1	nxp,os-timer
	on-chip	ARMv8-M System Tick1	arm,armv8m-systick
USB	on-chip	NXP LPCIP3511 USB device mode1	nxp,lpcip3511
Watchdog	on-chip	LPC Windowed Watchdog Timer1 1	nxp,lpc-wwdt

Connections and IOs

The MIMXRT595 SoC has IOCON registers, which can be used to configure the functionality of a pin.

Name	Function	Usage
PIO0_2	USART0	USART RX
PIO0_1	USART0	USART TX
PIO0_14	GPIO	GREEN LED
PIO0_25	GPIO	SW0
PIO0_10	GPIO	SW1
PIO4_30	USART12	USART TX
PIO4_31	USART12	USART RX
PIO0_29	I2C	I2C SCL
PIO0_30	I2C	I2C SDA
PIO0_22	GPIO	FXOS8700 TRIGGER
PIO1_5	SPI	SPI MOSI
PIO1_4	SPI	SPI MISO
PIO1_3	SPI	SPI SCK
PIO1_6	SPI	SPI SSEL
PIO0_5	SCT0	SCT0 GPI0
PIO0_6	SCT0	SCT0 GPI1

System Clock

The MIMXRT595 EVK is configured to use the OS Event timer as a source for the system clock.

Serial Port

The MIMXRT595 SoC has 13 FLEXCOMM interfaces for serial communication. One is configured as USART for the console and the remaining are not used.

Fusion F1 DSP Core

You can build a Zephyr application for the RT500 DSP core by targeting the F1 SOC. Xtensa toolchain supporting RT500 DSP core is included in Zephyr SDK. To build the hello_world sample for the RT500 DSP core:

$ west build -b mimxrt595_evk/mimxrt595s/f1 samples/hello_world

For detailed instructions on how to debug DSP firmware, please refer to this document: Getting Started with Xplorer for EVK-MIMXRT595

Programming and Debugging

Build and flash applications as usual (see Building an Application and Run an Application for more details).

Configuring a Debug Probe

A debug probe is used for both flashing and debugging the board. This board is configured by default to use the LPC-Link2.

LPCLink2 JLink OnboardJLink ExternalLinkserver

1. Install the J-Link Debug Host Tools and make sure they are in your search path.

2. To connect the SWD signals to onboard debug circuit, install jumpers JP17, JP18 and JP19, if not already done (these jumpers are installed by default).

3. Follow the instructions in LPC-Link2 J-Link Onboard Debug Probe to program the J-Link firmware. Please make sure you have the latest firmware for this board.

Configuring a Console

Connect a USB cable from your PC to J40, and use the serial terminal of your choice (minicom, putty, etc.) with the following settings:

• Speed: 115200

• Data: 8 bits

• Parity: None

• Stop bits: 1

Flashing

Here is an example for the Hello World application. This example uses the J-Link Debug Host Tools as default.

# From the root of the zephyr repository
west build -b mimxrt595_evk/mimxrt595s/cm33 samples/hello_world
west flash

Open a serial terminal, reset the board (press the RESET button), and you should see the following message in the terminal:

*** Booting Zephyr OS v2.7 ***
Hello World! mimxrt595_evk

Debugging

Here is an example for the Hello World application. This example uses the J-Link Debug Host Tools as default.

# From the root of the zephyr repository
west build -b mimxrt595_evk/mimxrt595s/cm33 samples/hello_world
west debug

Open a serial terminal, step through the application in your debugger, and you should see the following message in the terminal:

*** Booting Zephyr OS v2.7 ***
Hello World! mimxrt595_evk

Troubleshooting

If the debug probe fails to connect with the following error, it’s possible that the image in flash is interfering and causing this issue.

Remote debugging using :2331
Remote communication error.  Target disconnected.: Connection reset by peer.
"monitor" command not supported by this target.
"monitor" command not supported by this target.
You can't do that when your target is `exec'
(gdb) Could not connect to target.
Please check power, connection and settings.

You can fix it by erasing and reprogramming the flash with the following steps:

1. Set the SW7 DIP switches to ON-ON-ON to prevent booting from flash.

2. Reset by pressing SW3

3. Run west debug or west flash again with a known working Zephyr application (example “Hello World”).

4. Set the SW5 DIP switches to OFF-OFF-ON to boot from flash.

5. Reset by pressing SW3

Support Resources for Zephyr

• NXP Zephyr Downstream Software Development Kit

• MCUXpresso for VS Code, wiki documentation and Zephyr lab guides

• NXP Zephyr Knowledge Hub

• NXP’s Zephyr landing page (including training resources)

• NXP Support Community forum for Zephyr