This is the documentation for the latest (main) development branch of Zephyr. If you are looking for the documentation of previous releases, use the drop-down menu on the left and select the desired version.

INTEL FPGA niosv_m


niosv_m board is based on Intel FPGA Design Store Nios® V/m Hello World Example Design system and this complete system is consisted of following IP blocks:

Nios® V/m Processor Intel® FPGA IP
On-Chip Memory Intel® FPGA IP

Nios® V/m hello world example design system

Prebuilt Nios® V/m hello world example design system is available in Intel FPGA Design store. -

For example, Arria10 Nios® V/m processor example design system prebuilt files can be downloaded from following link. -

ready_to_test/top.sof file is the prebuilt SRAM Object File for hello world example design system after the downloaded PAR files extracted successfully.

Create Nios® V/m processor example design system in FPGA

Please use Intel Quartus Programmer tool to program Nios® V/m processor based system into the FPGA and execute application.

In order to create the Nios® V/m processor inside the FPGA device, please download the generated .sof file onto the board with the following command.

quartus_pgm -c 1 -m JTAG -o "p;top.sof@1"
-c 1 is referring to JTAG cable number connected to the Host Computer.
@1 is referring to device index on the JTAG Chain and may differ for your board.
top.sof is referring to Nios® V/m processor based system SRAM Object File.

Download Zephyr elf file and run application

To download the Zephyr Executable and Linkable Format .elf file, please use the niosv-download command within Nios V Command Shell environment.

niosv-download -g <elf file>

Use the JTAG UART terminal to print the stdout and stderr of the Nios® V/m processor system.


Similar message shown below should be appeared in the JTAG UART terminal when using hello world sample code:

*** Booting Zephyr OS build zephyr-vn.n.nn  ***
Hello World! niosv_m