Agilex™ 5 SoC FPGA Development Kit
Intel® Agilex™ 5 SoC FPGA Development Kit
Overview
The Intel® Agilex™ 5 SoC FPGA Development Kit offers a complete design environment that includes both hardware and software for developing Intel® Agilex™ 5 E-Series based FPGA designs. This kit is recommended for developing custom ARM* processor-based SoC designs and ideal for intelligent applications at the edge, embedded and more.
Hardware
The Intel® Agilex™ 5 Development Kit supports the following physical features:
Intel® Agilex™ 5 E-Series FPGA, 50K-656K LEs integrated with multi-core ARM processors of Dual-core A55 and Dual-core A76
On-board 8 GB DDR5 memory
On-board JTAG Intel FPGA Download Cable II
QSPI flash daughtercard
Supported Features
The intel_socfpga_agilex5_socdk board supports the hardware features listed below.
- on-chip / on-board
- Feature integrated in the SoC / present on the board.
- 2 / 2
-
Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files. -
vnd,foo -
Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.
intel_socfpga_agilex5_socdk/agilex5 target
Type |
Location |
Description |
Compatible |
|---|---|---|---|
CPU |
on-chip |
ARM Cortex-A55 CPU2 |
|
on-chip |
ARM Cortex-A76 CPU2 |
||
Clock control |
on-chip |
Agilex5 clock controller node1 |
|
Counter |
on-chip |
||
DMA |
on-chip |
||
Ethernet |
on-chip |
Synopsys DesignWareCore XGMAC3 |
|
on-chip |
Synopsys DWC XGMAC MDIO SMA Driver node3 |
||
on-board |
Generic MII PHY1 |
||
Flash controller |
on-chip |
Cadence Nand flash controller1 |
|
Interrupt controller |
on-chip |
ARM Generic Interrupt Controller v31 |
|
on-chip |
GIC v3 Interrupt Translation Service1 |
||
Power management CPU operations |
on-chip |
Power State Coordination Interface (PSCI) version 1.11 |
|
Reset controller |
on-chip |
Intel SoC FPGA Reset Controller1 |
|
SDHC |
on-chip |
Cadence SDHC Controller1 |
|
Serial controller |
on-chip |
ns16550 UART1 |
|
Service in Platform |
on-chip |
SiP SVC driver instance on Intel Agilex SOC FPGA for SMC call1 |
|
System controller |
on-chip |
System Controller Registers R/W2 |
|
Timer |
on-chip |
per-core ARM architected timer1 |
|
Watchdog |
on-chip |
Synopsys Designware Watchdog5 |
Programming and Debugging
Zephyr Boot Flow
Zephyr image will need to be loaded by Intel Arm Trusted Firmware (ATF). ATF BL2 is the First Stage Boot Loader (FSBL) and ATF BL31 is the Run time resident firmware which provides services like SMC (Secure monitor calls) and PSCI (Power state coordination interface).
- Boot flow:
ATF BL2 (EL3) -> ATF BL31 (EL3) -> Zephyr (EL1)
- Intel Arm Trusted Firmware (ATF) can be downloaded from github:
Flashing
Zephyr image can be loaded in DDR memory at address 0x80000000 from SD Card or QSPI Flash or NAND in ATF BL2.
Debugging
The Intel® Agilex™ 5 SoC Development Kit includes one JTAG connector on board, connect it to Intel USB blaster download cables for debugging.
Zephyr applications running on the Cortex-A55/A76 core can be tested by observing UART console output.