Agilex SoC Development Kit
Intel Agilex SoC Development Kit
Overview
The Intel Agilex SoC Development Kit offers a complete design environment that includes both hardware and software for developing Intel Agilex F-Series FPGA designs. This kit is recommended for developing custom Arm* processor-based SoC designs and evaluating transceiver performance.
Hardware
The Intel Agilex SoC Development Kit supports the following physical features:
Intel Agilex F-Series FPGA, 1400 KLE, 2486A package integrate the quad-core Arm Cortex-A53 processor
On-board 8 GB DDR4 memory
On-board JTAG Intel FPGA Download Cable II
QSPI flash daughtercard
HPS OOBE daughtercard with UART and SD Card support
Supported Features
The intel_socfpga_agilex_socdk board supports the hardware features listed below.
- on-chip / on-board
- Feature integrated in the SoC / present on the board.
- 2 / 2
-
Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files. -
vnd,foo -
Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.
intel_socfpga_agilex_socdk/agilex target
Type |
Location |
Description |
Compatible |
|---|---|---|---|
CPU |
on-chip |
ARM Cortex-A53 CPU4 |
|
Clock control |
on-chip |
Agilex clock controller node1 |
|
Counter |
on-chip |
||
Flash controller |
on-chip |
Cadence Quad-SPI NOR flash controller1 |
|
on-board |
Micron QSPI Flash1 |
||
Interrupt controller |
on-chip |
ARM Generic Interrupt Controller v21 |
|
Serial controller |
on-chip |
ns16550 UART1 |
|
Service in Platform |
on-chip |
SiP SVC driver instance on Intel Agilex SOC FPGA for SMC call1 |
|
System controller |
on-chip |
System Controller Registers R/W1 |
|
Timer |
on-chip |
per-core ARM architected timer1 |
|
Watchdog |
on-chip |
Synopsys Designware Watchdog4 |
Programming and Debugging
Boot Flow
Zephyr image will need to be loaded by Intel Arm Trusted Firmware (ATF). ATF BL2 is first stage boot loader (FSBL) and ATF BL31 is second stage boot loader (SSBL).
Zephyr boot flow:
ATF BL2 (EL3) -> ATF BL31 (EL3) -> Zephyr (EL2->EL1)
Intel Arm Trusted Firmware (ATF) can be downloaded from github:
Flashing
Zephyr image can be loaded in DDR memory at address 0x10000000 from SD Card or QSPI Flash in ATF BL2.
Debugging
The Intel Agilex SoC Development Kit includes one JTAG connector on board, connect it to Intel USB blaster download cables for debugging.
Zephyr applications running on the Cortex-A53 core can be tested by observing UART console output.