OpenTitan Earl Grey

Overview

The OpenTitan Earl Grey chip is a low-power secure microcontroller that is designed for several use cases requiring hardware security. The OpenTitan Github [2] page contains HDL code, utilities, and documentation relevant to the chip.

Hardware

  • RV32IMCB RISC-V “Ibex” core

  • 128kB main SRAM

  • Fixed-frequency and AON timers

  • 32 x GPIO

  • 4 x UART

  • 3 x I2C

  • 2 x SPI host

  • 1 x SPI device

  • Various security peripherals

Detailed specification is on the OpenTitan Earl Grey Chip Datasheet [1].

Supported Features

The opentitan_earlgrey board supports the hardware features listed below.

on-chip / on-board
Feature integrated in the SoC / present on the board.
2 / 2
Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.
vnd,foo
Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

opentitan_earlgrey/opentitan target

Type

Location

Description

Compatible

CPU

on-chip

LowRISC Ibex RISC-V core1

lowrisc,ibex

Interrupt controller

on-chip

RISC-V CPU interrupt controller1

riscv,cpu-intc

on-chip

SiFive RISCV-V platform-local interrupt controller1

sifive,plic-1.0.0

MTD

on-chip

Flash node1

soc-nv-flash

Power management

on-chip

OpenTitan power management1

lowrisc,opentitan-pwrmgr

Serial controller

on-chip

OpenTitan UART1

lowrisc,opentitan-uart

SPI

on-chip

OpenTitan SPI controller2

lowrisc,opentitan-spi

Timer

on-chip

RISC-V Machine Timer1

riscv,machine-timer

Watchdog

on-chip

OpenTitan Always-On Timer driver1

lowrisc,opentitan-aontimer

Programming and Debugging

The opentitan_earlgrey board supports the runners and associated west commands listed below.

flash debug

First, build and install Verilator as described in the OpenTitan Verilator Setup [3] guide .

Building and Flashing

Here is an example for building the Hello World application. The following steps were tested on OpenTitan master branch @ 6a3c2e98.

# From the root of the zephyr repository
west build -b opentitan_earlgrey samples/hello_world

The OpenTitan Vchip_sim_tb tool can take the Zephyr .elf as input and place it in simulated flash. The OpenTitan test ROM will then run in simulation, read the manifest header from simulated flash, and begin executing Zephyr from the entry point.

$OT_HOME/bazel-bin/hw/build.verilator_real/sim-verilator/Vchip_sim_tb --verbose-mem-load \
-r $OT_HOME/bazel-out/k8-fastbuild-ST-2cc462681f62/bin/sw/device/lib/testing/test_rom/test_rom_sim_verilator.39.scr.vmem \
--meminit=otp,$OT_HOME/bazel-out/k8-fastbuild/bin/hw/ip/otp_ctrl/data/img_rma.24.vmem \
--meminit=flash,$ZEPHYR_PATH/build/zephyr/zephyr.elf

UART output:

I00000 test_rom.c:135] Version: earlgrey_silver_release_v5-9599-g6a3c2e988, Build Date: 2023-01-17 16:02:09
I00001 test_rom.c:237] Test ROM complete, jumping to flash (addr: 20000384)!
*** Booting Zephyr OS build zephyr-v3.2.0-3494-gf0729b494b98 ***
Hello World! opentitan_earlgrey

References