SC-OBC Module V1

Overview

The Space Cubics [1] OBC Module V1 (SC-OBC Module V1) is an onboard computer for space missions that require reliable real-time control and edge processing. It is built around an AMD Versal Adaptive SoC and a Microchip IGLOO2 FPGA, and is designed for harsh environments such as Earth orbit and lunar missions.

On the Versal side, the SC-OBC V1 leverages the device’s heterogeneous architecture, combining general-purpose processors, programmable logic, and a vector processor, to run on-orbit workloads such as object detection, image compression/segmentation, and high-speed signal processing, while keeping flight-critical tasks under Zephyr RTOS’s predictable scheduling model.

On the IGLOO2 side, the SC-OBC V1 uses the device as the board’s safety processor, supervising the main system, providing independent watchdog and fault-management paths, and coordinating safe-mode transitions to improve fault tolerance.

Hardware

Supported Features

The scobc_v1 board supports the hardware features listed below.

on-chip / on-board
Feature integrated in the SoC / present on the board.
2 / 2
Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.
vnd,foo
Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

scobc_v1/versal_rpu target

Type

Location

Description

Compatible

CPU

on-chip

ARM Cortex-R5F CPU1

arm,cortex-r5f

Interrupt controller

on-chip

ARM Generic Interrupt Controller v11

arm,gic-v1

Serial controller

on-chip

ARM SBSA UART2

arm,sbsa-uart

Timer

on-chip

Xilinx PS Triple-Timer Counter13

xlnx,ttcps

System Clock

This board provides a 50 MHz reference oscillator for clock generation. The RPU (Cortex-R5F) runs at 600 MHz by default on this board.

In Zephyr, the “system clock” is the kernel’s tick base. By default it’s 100 Hz for periodic-tick builds and 10 kHz (10000 Hz) for tickless builds. See CONFIG_SYS_CLOCK_TICKS_PER_SEC for more details.

Serial Port

The SC-OBC Module V1 has multiple UART ports. The primary ports are routed to the FT4232H on the evaluation board, so when you connect the board to your PC with a USB Type-C cable, your development machine will enumerate them.

  • Port A is used for JTAG.

  • Port B connects to UART0 via LPD MIO pin 0 (RXD) and pin 1 (TXD) on Bank 502.

  • Port C connects to UART1 via LPD MIO pin 4 (TXD) and pin 5 (RXD) on Bank 502. For Zephyr on Versal RPU, UART1 is selected as the default console in scobc_v1_versal_rpu.dts. On a Linux host, the console typically appears as something like /dev/ttyUSB2 (device index may vary).

  • Port D connects to IGLOO2.

Programming and Debugging

The scobc_v1 board supports the runners and associated west commands listed below.

flash debug robot rtt attach simulate debugserver
xsdb ✅ (default) ✅ (default) ✅ ✅ ✅ ✅ ✅

Flashing

Here is an example for building and flashing the Hello World application for the board:

# From the root of the zephyr repository
west build -b scobc_v1 samples/hello_world
west flash --pdi /path/to/your.pdi

After flashing, you should see message similar to the following in the terminal:

*** Booting Zephyr OS build v4.2.0 ***
Hello World! scobc_v1/versal_rpu

References