BL604E IOT DVK development board

Overview

BL602/BL604 is a Wi-Fi+BLE chipset introduced by Bouffalo Lab, which is used for low power consumption and high performance application development. The wireless subsystem includes 2.4G radio, Wi-Fi 802.11b/g/n and BLE 5.0 baseband/MAC design. The microcontroller subsystem includes a 32-bit RISC CPU with low power consumption, cache and memory. The power management unit controls the low power consumption mode. In addition, it also supports various security features. The external interfaces include SDIO, SPI, UART, I2C, IR remote, PWM, ADC, DAC, PIR and GPIO.

The BL602 Development Board features a SiFive E24 32 bit RISC-V CPU with FPU, it supports High Frequency clock up to 192Mhz, have 128k ROM, 276kB RAM, 2.4 GHz WIFI 1T1R mode, support 20 MHz, data rate up to 72.2 Mbps, BLE 5.0 with 2MB phy. It is a secure MCU which supports Secure boot, ECC-256 signed image, QSPI/SPI Flash On-The-Fly AES Decryption and PKA (Public Key Accelerator).

Hardware

For more information about the Bouffalo Lab BL-60x MCU:

Supported Features

The bl604e_iot_dvk board supports the hardware features listed below.

on-chip / on-board: Feature integrated in the SoC / present on the board.
2 / 2: Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.
vnd,foo: Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

`bl604e_iot_dvk/bl604e20q2i` target

Type	Location	Description	Compatible
CPU	on-chip	SiFive E24 Standard Core CPU1	`sifive,e24`
ADC	on-chip	Bouffalolab ADC1	`bflb,adc`
Cache	on-chip	Bouffalo Lab L1C cache control1	`bflb,l1c`
Clock control	on-chip	Generic fixed-rate clock provider3 1	`fixed-clock`
	on-chip	Bouffalolab F32K clock1	`bflb,f32k`
	on-chip	Bouffalolab PLL settings1	`bflb,pll`
	on-chip	Bouffalolab Root Clock Represents both FCLK and HCLK depending on their presence, which should be kept the same1	`bflb,root-clk`
	on-chip	The BCLK clock, or peripheral clock Source -> / divider -> This Clock1	`bflb,bclk`
	on-chip	BFLB Flash Clock Source -> divider -> CLK Only has settings for Bank 1 on BL61x (boot flash) at the moment1	`bflb,flash-clk`
	on-chip	Bouffalolab BL60x Clock Controller1	`bflb,bl60x-clock-controller`
Counter	on-chip	Bouffalo Lab General Purpose Timer Block1	`bflb,timer`
	on-chip	Bouffalo Lab Timer Channel (Counter)2	`bflb,timer-channel`
	on-chip	Bouffalo Lab RTC Counter (HBN-based)1	`bflb,rtc`
Cryptographic accelerator	on-chip	Bouffalo Lab SEC Engine TRNG (True Random Number Generator)1	`bflb,sec-eng-trng`
	on-chip	Bouffalo Lab SEC Engine SHA hardware accelerator1	`bflb,sec-eng-sha`
	on-chip	Bouffalo Lab SEC Engine AES hardware accelerator1	`bflb,sec-eng-aes`
DMA	on-chip	Bouffalo Lab DMA1	`bflb,dma`
Flash controller	on-chip	Bouffalolab Flash Controller1	`bflb,flash-controller`
GPIO & Headers	on-chip	Bouffalo Lab BL60x and BL70x GPIO node1	`bflb,bl60x_70x-gpio`
I2C	on-chip	Bouffalolab I2C interface1	`bflb,i2c`
Input	on-chip	Bouffalolab Infrared Receiver Peripheral Wire the output of a diode like VS1838B to the specified GPIO pin1	`bflb,irx`
Interrupt controller	on-chip	RISC-V CPU interrupt controller1	`riscv,cpu-intc`
Interrupt controller	on-chip	RISC-V Core Local Interrupt Controller CLIC Pre-Standard v0.91	`sifive,clic-draft`
MTD	on-board	Flash node1	`soc-nv-flash`
MTD	on-board	Fixed partitions of a flash (or other non-volatile storage) memory1	`fixed-partitions`
Pin control	on-chip	Bouffalo Lab Pinctrl node1	`bflb,pinctrl`
Power management	on-chip	Bouffalolab Power Controller1	`bflb,power-controller`
PWM	on-chip	Bouffalolab PWM 11	`bflb,pwm-1`
Regulator	on-chip	Bouffalolab HBN SoC (CPU, Memory, etc) voltage regulator It is a LDO with a canonical voltage of 1.10v It has two modes, but they are only switched between when going into sleep mode and do not share settings areas1	`bflb,soc-regulator`
	on-chip	Bouffalolab HBN RT (RTC) voltage regulator It is a LDO with a canonical voltage of 1.10v It has two modes, but they are only switched between when going into sleep mode and do not share settings areas1	`bflb,rt-regulator`
	on-chip	Bouffalolab HBN AON (Always ON section) voltage regulator It is a LDO with a canonical voltage of 1.10v It has two modes, but they are only switched between when going into sleep mode and do not share settings areas1	`bflb,aon-regulator`
Serial controller	on-chip	Bouffalo Lab UART1 1	`bflb,uart`
SPI	on-chip	Bouffalolab SPI1	`bflb,spi`
SRAM	on-chip	Generic on-chip SRAM2	`mmio-sram`
System controller	on-chip	BouffaloLab Efuse1	`bflb,efuse`
Timer	on-chip	RISC-V Machine Timer1	`riscv,machine-timer`
Watchdog	on-chip	Bouffalo Lab Watchdog Timer1	`bflb,wdt`

System Clock

The BL604E Development Board is configured to run at max speed (192MHz).

Serial Port

The bl604e_iot_dvk board uses UART0 as default serial port. It is connected to USB Serial converter and port is used for both program and console.

Programming and Debugging

The bl604e_iot_dvk board supports the runners and associated west commands listed below.

	flash	debug	attach	rtt	debugserver
bflb_mcu_tool	✅ (default)
openocd	✅	✅ (default)	✅	✅	✅

Samples

Build the Zephyr kernel and the Hello World sample application:

# From the root of the zephyr repository
west build -b bl604e_iot_dvk samples/hello_world
west flash

Run your favorite terminal program to listen for output. Under Linux the terminal should be /dev/ttyACM0. For example:
```
$ minicom -D /dev/ttyACM0 -o
```
The -o option tells minicom not to send the modem initialization string. Connection should be configured as follows:
- Speed: 115200
- Data: 8 bits
- Parity: None
- Stop bits: 1
Then, press and release RST button
```
*** Booting Zephyr OS build v4.1.0 ***
Hello World! bl604e_iot_dvk/bl604e20q2i
```

Congratulations, you have bl604e_iot_dvk configured and running Zephyr.