Erbium

Overview

The Erbium board configuration is a minimal Zephyr port to a single core on the 16-core Erbium platform, part of the OpenHW Foundation CORE-ET project. It exposes one 64-bit RISC-V hart, an MRAM memory region and controller, a PLIC, a machine timer, and a polling UART console. This configuration targets the original UART revision supported by the public et-platform functional simulator.

Hardware

The board configuration describes the following hardware:

64-bit RISC-V hart with the rv64imc_zicsr_zifencei ISA extensions
16 MiB MRAM memory region
Platform-Level Interrupt Controller
RISC-V machine timer
Nekko Shakti UART, using 32-bit accesses at eight-byte register intervals

Supported Features

The erbium board supports the hardware features listed below.

on-chip / on-board: Feature integrated in the SoC / present on the board.
2 / 2: Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.
vnd,foo: Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

`erbium/erbium` target

On-target memory for this board target: 16776704 B of RAM, N/A of Flash.

Type	Location	Description	Compatible
CPU	on-chip	Generic RISC-V CPU1	`riscv`
Interrupt controller	on-chip	RISC-V CPU interrupt controller1	`riscv,cpu-intc`
Interrupt controller	on-chip	SiFive RISCV-V platform-local interrupt controller1	`sifive,plic-1.0.0`
Memory controller	on-chip	Erbium AXI-to-MRAM bridge and per-bank controller registers1	`openhwgroup,erbium-mram-controller`
Serial controller	on-chip	Original Erbium integration of the Nekko Shakti UART, with 32-bit accesses at eight-byte intervals, InterruptEn at 0x30 and Rx_Threshold at 0x401	`openhwgroup,shakti-uart-v1`
SRAM	on-chip	Generic on-chip SRAM1	`mmio-sram`
Timer	on-chip	RISC-V Machine Timer1	`riscv,machine-timer`

The UART supports polling input and output at 115200 baud, 8 data bits, no parity, and one stop bit. Interrupt-driven and asynchronous UART operations, runtime line configuration, and hardware flow control are not implemented.

Floating-point support

Erbium’s floating-point unit implements only part of the standard F extension. Single-precision division, square root, and conversions between single-precision values and 64-bit integers raise M-code emulation exception 30. The hardware also flushes denormal inputs and results to zero, as described in the CPU programming model.

The devicetree therefore omits the F extension, and this port uses software floating point with the lp64 ABI. Hardware FPU support and FPU context sharing are unavailable. Applications and libraries must be built for rv64imc_zicsr_zifencei with the lp64 ABI; binaries built for lp64f are incompatible. The port does not emulate exception 30.

UART revision

The openhwgroup,shakti-uart-v1 compatible identifies the original Erbium integration described by the original UART register documentation. It has InterruptEn at offset 0x30 and Rx_Threshold at offset 0x40. The driver configures the baud divisor, line format, delay, interrupt enable, and receive threshold during initialization. To transmit a character, it waits for room in the transmit FIFO and writes the data register, following the documented program flow.

The generic shakti,uart driver uses four-byte register intervals and mixed 16-bit and 32-bit accesses. Later Erbium RTL also has a different interrupt register layout, described in the revised UART documentation. Neither register layout is compatible with this board configuration.

Memory and boot requirements

Zephyr executes from the MRAM window at 0x40000200. The first 512 bytes of the 16 MiB window are reserved for the boot flow. The MRAM controller is described at 0x02001000, with PLIC interrupt 1, following the CPU memory map and platform interrupt map; the data window is its child node. The data window is directly readable, writable, and executable, and the only on-chip SRAM is 4 KiB at 0x0200C000, so the MRAM window is used as Zephyr’s SRAM region. MRAM controller initialization, ECC handling, and power management remain the responsibility of the boot firmware; there is no Zephyr MRAM driver.

The boot firmware must enter hart 0 in machine mode with MRAM initialized, the other harts parked, and the UART enabled through SystemConfig bit 6. The board configuration assumes a 400 MHz UART input clock and a 2 MHz machine timer. Adjust uart0.clock-frequency and /cpus/timebase-frequency in a devicetree overlay when the boot firmware uses different clocks.

Erbium does not implement WFI. The SoC idle functions poll for an enabled pending interrupt while global interrupts are masked, then restore interrupt delivery. This preserves the idle wakeup contract without using WFI.

Programming and Debugging

The erbium board supports the runners and associated west commands listed below.

	flash	debug

Building

Applications for the erbium board configuration can be built in the usual way. For example, with the Hello World sample:

# From the root of the zephyr repository
west build -b erbium samples/hello_world

Flashing and Running

No upstream runner is provided for this board yet. Run the ELF with erbium_emu from et-platform. The original UART model is available at revision 836a4ab600e93c3059bb58c898edbc37744cd8d0. Build the repository’s erbium-hal package and then sw-sysemu with that package on CMAKE_PREFIX_PATH.

From the Zephyr application directory, with erbium_emu on PATH:

erbium_emu -elf_load build/zephyr/zephyr.elf \
  -reset_pc 0x40000200 -minions 1 -single_thread \
  -mem_write32 0x02000008,0x44 -max_cycles 2000000 \
  -uart_rx_file /dev/null -uart_tx_file uart.log
cat uart.log

The SystemConfig write enables the UART and keeps the watchdog disabled in the simulator. Loading the ELF and setting its entry point bypasses ROM boot. The UART log should contain Hello World! erbium/erbium. The simulator reports a cycle-limit error after the sample enters idle; judge the sample by its UART output, not the simulator’s exit code.

UART tests

Build the polling API test with Twister:

./scripts/twister -p erbium -T tests/drivers/uart/uart_basic_api \
  -s drivers.uart.basic_api.poll --build-only

Run the resulting zephyr.elf with the same simulator options, increasing -max_cycles to 10000000. Supply a file containing a short line, for example erbium-rx followed by a newline, through -uart_rx_file. The input must fit the 16-byte receive FIFO. Check that the line is echoed and that the UART log ends with PROJECT EXECUTION SUCCESSFUL. Runtime UART configuration is unsupported; the generic test accepts that API result.

The functional model verifies software register accesses and console I/O. It does not validate physical baud timing or silicon behavior.