Nexys Video (Ganga SoC)

Overview

SHAKTI is India’s first indigenous open-source RISC-V processor initiative, developed by RISE group at IIT Madras. Ganga is a 64-bit (RV64IMAC) SHAKTI SoC, providing CLINT and PLIC interrupt controllers, a machine timer, and a UART used for the Zephyr console.

This board target runs the Ganga SoC as a softcore on the Digilent Nexys Video, a Xilinx Artix-7 FPGA board. Applications can be loaded onto the FPGA over JTAG via the board’s on board USB JTAG chip.

The complete hardware sources, together with instructions for building the bitstream and loading it onto the Nexys Video, are available (see the references below)

See the following references for more information:

Hardware

  • Ganga CPU with the RV64IMAC instruction set, running at 40 MHz

  • CLINT and PLIC interrupt controllers with a machine timer

  • 256 MB of RAM

  • UART, used for the Zephyr console at 19200 baud

  • JTAG via the on board USB JTAG chip

Supported Features

The nexys_ganga board supports the hardware features listed below.

on-chip / on-board
Feature integrated in the SoC / present on the board.
2 / 2
Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.
vnd,foo
Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

Programming and Debugging

The nexys_ganga board supports the runners and associated west commands listed below.

flash debug

The FPGA must be configured with the Ganga bitstream before loading any Zephyr application, refer to the SHAKTI gc2025 sources for building and loading the bitstream. Once the bitstream is loaded Zephyr applications are built and flashed as usual

Configuring a Console

The board provides a console on UART0. Use the following settings with your serial terminal of choice:

  • Speed: 19200

  • Data: 8 bits

  • Parity: None

  • Stop bits: 1

The baud rate can be changed via the current-speed property of the uart0 devicetree node.

Flashing

west flash is supported via the openocd runner. Here is an example for the Hello World application:

# From the root of the zephyr repository
west build -b nexys_ganga samples/hello_world
west flash

After flashing, you should see a message similar to the following in the terminal:

*** Booting Zephyr OS build ... ***
Hello World! nexys_ganga/ganga

The application is loaded into the FPGA block RAM and is not persisted, it reverts the next time the FPGA is reconfigured.

Debugging

west debug is supported via the openocd runner. Here is an example for the Hello World application:

# From the root of the zephyr repository
west build -b nexys_ganga samples/hello_world
west debug

References