ElemRV Flask-H

Overview

ElemRV-H is the smallest and most area-optimized design in the ElemRV family, built on the Hydrogen platform. It provides a minimal feature set, targeting applications where resource constraints are the primary concern.

For more details, refer to the official GitHub Project.

Supported Features

The elemrv_flask_h board supports the hardware features listed below.

on-chip / on-board: Feature integrated in the SoC / present on the board.
2 / 2: Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.
vnd,foo: Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

`elemrv_flask_h/elemrv_h` target

On-target memory for this board target: 8 KiB of RAM, 512 KiB of Flash.

Type	Location	Description	Compatible
CPU	on-chip	VexiiRiscv RISC-V CPU1	`spinalhdl,vexiiriscv`
Flash controller	on-chip	Aesc Silicon SPI flash controller1	`aesc,spi-flash-controller`
GPIO & Headers	on-chip	Aesc Silicon GPIO1	`aesc,gpio`
Interrupt controller	on-chip	RISC-V CPU interrupt controller1	`riscv,cpu-intc`
Interrupt controller	on-chip	SiFive RISCV-V platform-local interrupt controller1	`sifive,plic-1.0.0`
LED	on-board	Group of GPIO-controlled LEDs1	`gpio-leds`
MTD	on-board	Flash node1	`soc-nv-flash`
Pin control	on-chip	Aesc pin controller1	`aesc,pinctrl`
Serial controller	on-chip	Aesc Silicon UART1	`aesc,uart`
SRAM	on-board	Generic on-chip SRAM1	`mmio-sram`
Timer	on-chip	RISC-V Machine Timer1	`riscv,machine-timer`

System Clock

The system clock for the RISC-V core is set to 50 MHz. This value is specified in the cpu0 devicetree node using the clock-frequency property.

CPU

ElemRV-H integrates a VexiiRiscv RISC-V core with the following ISA extensions:

Zicsr – Control and Status Register operations
Zifencei – Instruction-fetch fence

The complete ISA string for this CPU is: RV32I_Zicsr_Zifencei

Hart-Level Interrupt Controller (HLIC)

Each CPU core is equipped with a Hart-Level Interrupt Controller, configurable through Control and Status Registers (CSRs).

Machine Timer

A RISC-V compliant machine timer is enabled by default.

Serial

The UART (Universal Asynchronous Receiver-Transmitter) interface is a configurable serial communication peripheral used for transmitting and receiving data.

By default, uart0 operates at a baud rate of 115200, which can be adjusted via the ElemRV device tree.

To evaluate the UART interface, build and run the following sample:

# From the root of the zephyr repository
west build -b elemrv_flask_h samples/hello_world

Pin Multiplexer

The pin multiplexer allows each pin to be assigned to one of multiple peripheral functions. The following table lists all available pin assignments:

Pin	Option 0	Option 1
0	gpio0_0	pwm0_out_0
1	gpio0_1	pio0_0
2	gpio0_2	pio0_1
3	gpio0_3	pio0_2
4	uart0_tx	gpio0_4
5	uart0_rx	gpio0_5
6	uart0_cts	gpio0_6
7	uart0_rts	gpio0_7
8	gpio0_8	pwm0_comp_0
9	gpio0_9	i2c0_scl
10	gpio0_10	i2c0_sda
11	gpio0_11	i2c0_interrupt_0

Note

PWM, PIO, and I2C drivers are not yet supported in Zephyr.

GPIO

The GPIO (General-Purpose Input/Output) interface with tri-state pins is a digital interface that allows each pin to be configured as either an input or an output, with additional control for setting the direction of data flow.

The Blinky sample provides a simple way to explore how a GPIO can be used to control an external LED.

# From the root of the zephyr repository
west build -b elemrv_flask_h samples/basic/blinky