XT-ZB1 Zigbee 3.0 and BLE 5.0 Coexistence Module Development Kit

Overview

XT-ZB1 Zigbee 3.0 and BLE 5.0 coexistence Module is a highly integrated single-chip solution providing Zigbee and BLE in a single chip. It also provides a bunch of configurable GPIO, which are configured as digital peripherals for different applications and control usage.

The XT-ZB1 Module use BL702 as Zigbee and BLE coexistence soc chip. The embedded memory configuration provides simple application developments.

Hardware

For more information about the Bouffalo Lab BL702 MCU:

Supported Features

The dt_xt_zb1_devkit board supports the hardware features listed below.

on-chip / on-board: Feature integrated in the SoC / present on the board.
2 / 2: Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.
vnd,foo: Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

`dt_xt_zb1_devkit/bl702c10q2h` target

Type	Location	Description	Compatible
CPU	on-chip	SiFive E24 Standard Core CPU1	`sifive,e24`
ADC	on-chip	Bouffalolab ADC1	`bflb,adc`
Bluetooth	on-chip	Bluetooth HCI for Bouffalo Lab BL70X1	`bflb,bl70x-bt-hci`
Cache	on-chip	Bouffalo Lab L1C cache control1	`bflb,l1c`
Clock control	on-chip	Generic fixed-rate clock provider3 1	`fixed-clock`
	on-chip	Bouffalolab F32K clock1	`bflb,f32k`
	on-chip	The BL70x/L DLL1	`bflb,bl70x_l-dll`
	on-chip	Bouffalolab Root Clock Represents both FCLK and HCLK depending on their presence, which should be kept the same1	`bflb,root-clk`
	on-chip	The BCLK clock, or peripheral clock Source -> / divider -> This Clock1	`bflb,bclk`
	on-chip	BFLB Flash Clock Source -> divider -> CLK Only has settings for Bank 1 on BL61x (boot flash) at the moment1	`bflb,flash-clk`
	on-chip	Bouffalolab BL70x(L) Clock Controller1	`bflb,bl70x_l-clock-controller`
Counter	on-chip	Bouffalo Lab General Purpose Timer Block1	`bflb,timer`
	on-chip	Bouffalo Lab Timer Channel (Counter)2	`bflb,timer-channel`
	on-chip	Bouffalo Lab RTC Counter (HBN-based)1	`bflb,rtc`
Cryptographic accelerator	on-chip	Bouffalo Lab SEC Engine TRNG (True Random Number Generator)1	`bflb,sec-eng-trng`
	on-chip	Bouffalo Lab SEC Engine SHA hardware accelerator1	`bflb,sec-eng-sha`
	on-chip	Bouffalo Lab SEC Engine AES hardware accelerator1	`bflb,sec-eng-aes`
DMA	on-chip	Bouffalo Lab DMA1	`bflb,dma`
Flash controller	on-chip	Bouffalolab Flash Controller1	`bflb,flash-controller`
GPIO & Headers	on-chip	Bouffalo Lab BL60x and BL70x GPIO node1	`bflb,bl60x_70x-gpio`
I2C	on-chip	Bouffalolab I2C interface1	`bflb,i2c`
Input	on-chip	Bouffalolab Infrared Receiver Peripheral Wire the output of a diode like VS1838B to the specified GPIO pin1	`bflb,irx`
Interrupt controller	on-chip	RISC-V CPU interrupt controller1	`riscv,cpu-intc`
Interrupt controller	on-chip	RISC-V Core Local Interrupt Controller CLIC Pre-Standard v0.91	`sifive,clic-draft`
MTD	on-board	Flash node1	`soc-nv-flash`
MTD	on-board	Fixed partitions of a flash (or other non-volatile storage) memory1	`fixed-partitions`
Pin control	on-chip	Bouffalo Lab Pinctrl node1	`bflb,pinctrl`
Power management	on-chip	Bouffalolab Power Controller1	`bflb,power-controller`
PWM	on-chip	Bouffalolab PWM 11	`bflb,pwm-1`
Regulator	on-chip	Bouffalolab HBN SoC (CPU, Memory, etc) voltage regulator It is a LDO with a canonical voltage of 1.10v It has two modes, but they are only switched between when going into sleep mode and do not share settings areas1	`bflb,soc-regulator`
	on-chip	Bouffalolab HBN RT (RTC) voltage regulator It is a LDO with a canonical voltage of 1.10v It has two modes, but they are only switched between when going into sleep mode and do not share settings areas1	`bflb,rt-regulator`
	on-chip	Bouffalolab HBN AON (Always ON section) voltage regulator It is a LDO with a canonical voltage of 1.10v It has two modes, but they are only switched between when going into sleep mode and do not share settings areas1	`bflb,aon-regulator`
Serial controller	on-chip	Bouffalo Lab UART1 1	`bflb,uart`
SPI	on-chip	Bouffalolab SPI1	`bflb,spi`
SRAM	on-chip	Generic on-chip SRAM3	`mmio-sram`
System controller	on-chip	BouffaloLab Efuse1	`bflb,efuse`
Timer	on-chip	RISC-V Machine Timer1	`riscv,machine-timer`
USB	on-chip	Bouffalo Lab USB 1.1 Full-Speed device controller (v1 block)1	`bflb,udc-1`
Watchdog	on-chip	Bouffalo Lab Watchdog Timer1	`bflb,wdt`

System Clock

The XT-ZB1 board is configured to run at max speed by default (144 MHz).

Serial Port

The dt_xt_zb1_devkit board uses UART0 as default serial port. It is connected to USB Serial converter and port is used for both program and console.

Programming and Debugging

The dt_xt_zb1_devkit board supports the runners and associated west commands listed below.

	flash	debug	rtt	attach	debugserver
bflb_mcu_tool	✅ (default)
openocd	✅	✅ (default)	✅	✅	✅

Samples

Build the Zephyr kernel and the Hello World sample application:

# From the root of the zephyr repository
west build -b dt_xt_zb1_devkit samples/hello_world
west flash

Run your favorite terminal program to listen for output. Under Linux the terminal should be /dev/ttyUSB0. For example:
```
$ screen /dev/ttyUSB0 115200
```
Connection should be configured as follows:
- Speed: 115200
- Data: 8 bits
- Parity: None
- Stop bits: 1
Then, press and release RST button
```
*** Booting Zephyr OS build v4.2.0-1031-g63c9db88d01a ***
Hello World! dt_xt_zb1_devkit/bl702c10q2h
```

Congratulations, you have dt_xt_zb1_devkit configured and running Zephyr.