LiteX VexiiRiscv

Board Overview

Name:

litex_vexiiriscv

Vendor:

EnjoyDigital

Status:

Not actively maintained

Architecture:

riscv

SoC:

litex_vexiiriscv

Browse board sources

Warning

This board is not a fixed piece of hardware, it is a soft SoC that is generated by the LiteX SoC Builder and may change at any time. The memory map, the set of peripherals, their base addresses and their configuration are all determined when the bitstream is generated, so a SoC built from a different LiteX revision or with a different configuration will most likely not match the devicetree shipped with this board.

The in-tree board definition is therefore only a snapshot of one specific configuration. Whenever your SoC does not match it exactly, generate a devicetree and Kconfig overlay for your build with litex_json2dts_zephyr.py (see Bitstream generation) instead of relying on the in-tree files, and expect the in-tree files to change without any backwards compatibility guarantees.

LiteX VexiiRiscv is an example of a system on a chip (SoC) that consists of a VexiiRiscv processor and additional peripherals. This setup can be generated using the LiteX SoC Builder and can be used on various FPGA chips. The bitstream (FPGA configuration file) can be obtained using both vendor-specific and open-source tools.

The litex_vexiiriscv board configuration in Zephyr is meant for the LiteX VexiiRiscv SoC implementation generated for the Efinix Titanium Ti375 C529 Development Kit.

LiteX is based on Migen/MiSoC SoC builder and provides ready-made system components such as buses, streams, interconnects, common cores, and CPU wrappers to create SoCs easily. The tool contains mechanisms for integrating, simulating, and building various designs that target multiple chips of different vendors. More information about the LiteX project can be found on LiteX’s website.

VexiiRiscv is a implementation of the RISC-V CPU architecture written in the SpinalHDL. The implementation is optimized for FPGA chips. More information about the project can be found on VexiiRiscv’s website.

To run the ZephyrOS on the VexiiRiscv CPU, it is necessary to prepare the bitstream for the FPGA on a Efinix Titanium Ti375 C529 Development Kit.

Supported Features

The litex_vexiiriscv board supports the hardware features listed below.

on-chip / on-board

Feature integrated in the SoC / present on the board.

2 / 2

Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.

vnd,foo

Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

litex_vexiiriscv/litex_vexiiriscv target

On-target memory for this board target: 1 GiB of RAM, N/A of Flash.

Type	Location	Description	Compatible
CPU	on-board	VexiiRiscv core with the standard configuration as used by LiteX1	litex,vexiiriscv-standard
Ethernet	on-board	LiteX LiteEth MDIO bitbang driver1	litex,liteeth-mdio
	on-board	Generic MII PHY1	ethernet-phy
	on-board	LiteX Ethernet1	litex,liteeth
Interrupt controller	on-board	RISC-V CPU interrupt controller1	riscv,cpu-intc
	on-board	SiFive RISCV-V platform-local interrupt controller1	sifive,plic-1.0.0
MTD	on-board	Properties supporting Zephyr spi-nor flash driver (over the Zephyr SPI API) control of serial flash memories using the standard M25P80-based command set1	jedec,spi-nor
RISC-V architecture	on-board	LiteX SoC Controller driver1	litex,soc-controller
SDHC	on-board	LiteX LiteSDCard SDHC2	litex,mmc
Serial controller	on-board	LiteX UART1	litex,uart
SPI	on-board	LiteX SPI LiteSPI Controller1	litex,spi-litespi
SRAM	on-board	Generic on-chip SRAM1	mmio-sram
Timer	on-board	RISC-V Machine Timer1	riscv,machine-timer
Watchdog	on-board	LiteX watchdog1	litex,watchdog

Bitstream generation

The bitstream is generated using the official LiteX repository. Because the generated SoC does not necessarily match the devicetree shipped with this board, you should always generate a devicetree and Kconfig overlay along with it.

1. Create a virtual environment and activate it:

   python3 -m venv .venv
   source .venv/bin/activate
   

2. Install Migen/LiteX and the LiteX’s cores:

   wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py
   chmod +x litex_setup.py
   ./litex_setup.py --init --install --user (--user to install to user directory) --config=(minimal, standard, full)
   

3. Install the RISC-V toolchain:

   pip3 install meson ninja
   ./litex_setup.py --gcc=riscv
   

4. Build the target:

   ./litex-boards/litex_boards/targets/efinix_ti375_c529_dev_kit.py --cpu-type=vexiiriscv --build
   

5. Generate the dts and config overlay:

   ./litex/litex/tools/litex_json2dts_zephyr.py --dts overlay.dts --config overlay.config csr.json
   

Programming and booting

Building

Applications for the litex_vexiiriscv board configuration can be built as usual (see Building an Application), by setting the BOARD variable to litex_vexiiriscv and passing the overlays generated for your SoC:

west build -b litex_vexiiriscv path/to/app -DDTC_OVERLAY_FILE=path/to/overlay.dts

Booting

To upload the bitstream to the FPGA you can either use the --load option or the --flash option to program the SPI flash.

You can boot from a serial port using litex_term (replace ttyUSBX with your device) , e.g.:

litex_term /dev/ttyUSBX --speed 115200 --kernel zephyr.bin