AM62L TMDS62LEVM evaluation module (EVM)
Overview
The AM62L EVM board configuration is used by Zephyr applications that run on the TI AM62L platform. The board configuration provides support for:
ARM Cortex-A53 core and the following features:
General Interrupt Controller (GIC)
ARM Generic Timer (arch_timer)
On-chip SRAM (oc_sram)
UART interfaces (uart0 to uart6)
The board configuration also enables support for the semihosting debugging console.
See the TI AM62L Product Page for details.
Hardware
The AM62L EVM features the AM62L SoC, which is composed of a dual Cortex-A53 cluster. The following listed hardware specifications are used:
High-performance ARM Cortex-A53
Memory
160KB of SRAM
2GB of DDR4
Debug
XDS110 based JTAG
Supported Features
The am62l_evm board supports the hardware features listed below.
- on-chip / on-board
- Feature integrated in the SoC / present on the board.
- 2 / 2
-
Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files. -
vnd,foo -
Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.
am62l_evm/am62l3/a53 target
Type |
Location |
Description |
Compatible |
|---|---|---|---|
CPU |
on-chip |
ARM Cortex-A53 CPU2 |
|
Firmware |
on-chip |
SCMI (System Control and Management Interface) power domain protocol1 |
|
on-chip |
SCMI (System Control and Management Interface) clock protocol1 |
||
on-chip |
SCMI (System Control and Management Interface) SHMEM (shared memory)1 |
||
GPIO & Headers |
on-chip |
GPIO Controller for Davinci and Keystone devices5 |
|
I2C |
on-chip |
TI OMAP I2C Controller5 |
|
Interrupt controller |
on-chip |
ARM Generic Interrupt Controller v31 |
|
on-chip |
GIC v3 Interrupt Translation Service1 |
||
Pin control |
on-chip |
TI K3 Pin Controller1 |
|
Power management CPU operations |
on-chip |
Power State Coordination Interface (PSCI) version 1.11 |
|
Serial controller |
on-chip |
||
SPI |
on-chip |
TI Multi Channel SPI controller for OMAP and K3 SoCs4 |
|
SRAM |
on-chip |
Generic on-chip SRAM1 |
|
Timer |
on-chip |
TI Dual-Mode Timer2 |
|
on-chip |
per-core ARM architected timer1 |
||
Watchdog |
on-chip |
K3 Watchdog timer (RTI module) available in the K3 generation of processors2 |
Devices
System Clock
This board configuration uses a system clock frequency of 1250 MHz.
DDR RAM
The board has 2GB of DDR RAM available.
Serial Port
This board configuration uses a single serial communication channel with the MAIN domain UART (main_uart0).
SD Card
Download TI’s official WIC and flash the WIC file with an etching software onto an SD-card.
Copy the compiled zephyr.bin to the first FAT partition of the SD card and
plug the SD card into the board. Power it up and stop the u-boot execution at
prompt.
Use U-Boot to load and start zephyr.bin:
fatload mmc 1:1 0x82000000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0x82000000
The Zephyr application should start running on the A53 core.
Debugging
The board is equipped with an XDS110 JTAG debugger. To debug a binary, utilize the debug build target:
west build -b am62l_evm/am62l3/a53 <my_app>
west debug
Hint
To utilize this feature, you’ll need OpenOCD version 0.12 or higher. Due to the possibility of older versions being available in package feeds, it’s advisable to build OpenOCD from source.