AMD Versal APU Development Board

Overview

This configuration provides support for the APU (Application Processing Unit) on AMD Versal devices. The APU can operate as follows:

  • Two independent Cortex-A72 cores

This processing unit is based on an ARM Cortex-A72 CPU, and it enables the following devices:

  • ARM GIC v3 Interrupt Controller

  • ARMv8 Generic Timer

  • SBSA UART

Hardware

Supported Features

The versal_apu board supports the hardware features listed below.

on-chip / on-board
Feature integrated in the SoC / present on the board.
2 / 2
Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.
vnd,foo
Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

versal_apu/versal_apu target

Type

Location

Description

Compatible

CPU

on-chip

ARM Cortex-A72 CPU1

arm,cortex-a72

Interrupt controller

on-chip

ARM Generic Interrupt Controller v31

arm,gic-v3

Power management CPU operations

on-chip

Power State Coordination Interface (PSCI) version 0.21

arm,psci-0.2

Serial controller

on-chip

ARM SBSA UART2

arm,sbsa-uart

SRAM

on-board

Generic on-chip SRAM1

mmio-sram

Timer

on-chip

per-core ARM architected timer1

arm,armv8-timer

Devices

System Timer

This board configuration uses a system timer tick frequency of 100 MHz.

Serial Port

This board configuration uses a single serial communication channel with the on-chip UART0.

Memories

Although Flash, DDR and OCM memory regions are defined in the DTS file, all the code plus data of the application will be loaded in the sram0 region, which points to the DDR memory. The OCM memory area is currently available for usage, although nothing is placed there by default.

Known Problems or Limitations

The following platform features are unsupported:

  • Only the first CPU in the APU subsystem is supported.

Programming and Debugging

The versal_apu board supports the runners and associated west commands listed below.

flash debug rtt robot attach debugserver simulate
xsdb ✅ (default) ✅ (default) ✅ ✅ ✅ ✅ ✅

For deployment on real Versal hardware, XSDB and a PDI file are required. The PDI file contains the hardware initialization and boot configuration needed for the physical device.

Build the application:

# From the root of the zephyr repository
west build -b versal_apu samples/hello_world

Flash to real hardware with PDI file:

west flash --runner xsdb --pdi /path/to/your.pdi --bl31 /path/to/your_bl31.elf

You should see the following message on the console:

Hello World! versal_apu/versal_apu

References

  1. ARMv8-A Architecture Reference Manual (ARM DDI 0487)

  2. Arm Cortex-A72 Core Technical Reference Manual (Doc ID 100095)

  3. AMD Versal Technical Reference Manual