versalnet_apu

Overview

This configuration provides support for the APU(A78), ARM processing unit on AMD Versal Net SOC, it can operate as following:

Four independent A78 clusters each having 4 A78 cores

This processing unit is based on an ARM Cortex-A78 CPU, it also enables the following devices:

ARM GIC v3 Interrupt Controller
Global Timer Counter
SBSA UART

Hardware

Supported Features

The versalnet_apu board supports the hardware features listed below.

on-chip / on-board: Feature integrated in the SoC / present on the board.
2 / 2: Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.
vnd,foo: Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

`versalnet_apu/amd_versalnet_apu` target

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-A78 CPU4	`arm,cortex-a78`
Interrupt controller	on-chip	ARM Generic Interrupt Controller v31	`arm,gic-v3`
Power management CPU operations	on-chip	Power State Coordination Interface (PSCI) version 1.11	`arm,psci-1.1`
Serial controller	on-chip	ARM SBSA UART2	`arm,sbsa-uart`
SRAM	on-board	Generic on-chip SRAM1	`mmio-sram`
Timer	on-chip	per-core ARM architected timer1	`arm,armv8-timer`

Devices

System Timer

This board configuration uses a system timer tick frequency of 100 MHz.

Serial Port

This board configuration uses a single serial communication channel with the on-chip UART0.

Memories

Although Flash, DDR and OCM memory regions are defined in the DTS file, all the code plus data of the application will be loaded in the sram0 region, which points to the DDR memory. The ocm0 memory area is currently available for usage, although nothing is placed there by default.

Known Problems or Limitations

The following platform features are unsupported:

Only the first cpu in the first cluster of the A78 subsystem is supported.

Programming and Debugging

The versalnet_apu board supports the runners and associated west commands listed below.

	flash	debug	rtt	simulate	robot	attach	debugserver
xsdb	✅ (default)	✅ (default)	✅	✅	✅	✅	✅

Build and flash in the usual way. Here is an example for the Hello World application.

# From the root of the zephyr repository
west build -b versalnet_apu samples/hello_world
west flash

You should see the following message on the console:

Hello World! versalnet_apu/amd_versalnet_apu

References

ARMv8‑A Architecture Reference Manual (ARM DDI 0487)
Arm Cortex‑A78 Core Technical Reference Manual (Doc ID 101430)