AMD Versal RPU Cortex-R5

Overview

This configuration provides support for the RPU (Real-time Processing Unit) on AMD Versal devices, it can operate as following:

  • Two independent R5 cores with their own TCMs (tightly coupled memories)

  • Or as a single dual lock step unit with the TCM.

This processing unit is based on an ARM Cortex-R5F CPU, it also enables the following devices:

  • ARM GIC v2 Interrupt Controller

  • Xilinx TTC (Triple Timer Counter)

  • SBSA UART

Hardware

Supported Features

The versal_rpu board supports the hardware features listed below.

on-chip / on-board
Feature integrated in the SoC / present on the board.
2 / 2
Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.
vnd,foo
Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

versal_rpu/versal_rpu target

Type

Location

Description

Compatible

CPU

on-chip

ARM Cortex-R5F CPU1

arm,cortex-r5f

Interrupt controller

on-chip

ARM Generic Interrupt Controller v11

arm,gic-v1

Serial controller

on-chip

ARM SBSA UART11

arm,sbsa-uart

SRAM

on-board

Generic on-chip SRAM1

mmio-sram

Timer

on-chip

Xilinx PS Triple-Timer Counter13

xlnx,ttcps

Devices

System Timer

This board configuration uses a system timer tick frequency of 100 MHz.

Serial Port

This board configuration uses a single serial communication channel with the on-chip UART0.

Memories

Although Flash, DDR and TCM memory regions are defined in the DTS file, all the code plus data of the application will be loaded in the sram0 region, which points to the DDR memory. The TCM memory area is currently available for usage, although nothing is placed there by default.

Known Problems or Limitations

The following platform features are unsupported:

  • Only the first core of the R5 subsystem is supported.

Programming and Debugging

The versal_rpu board supports the runners and associated west commands listed below.

flash debug attach reset robot rtt simulate debugserver
xsdb ✅ (default) ✅ (default) ✅ ✅ ✅ ✅ ✅ ✅

For deployment on real Versal hardware, XSDB and a PDI file are required. The PDI file contains the hardware initialization and boot configuration needed for the physical device.

Build the application:

# From the root of the zephyr repository
west build -b versal_rpu samples/hello_world

Flash to real hardware with PDI file:

west flash --runner xsdb --pdi /path/to/your.pdi

You should see the following message on the console:

Hello World! versal_rpu/versal_rpu

References

  1. ARMv7-A and ARMv7-R Architecture Reference Manual (ARM DDI 0406C ID051414)

  2. Cortex-R5 and Cortex-R5F Technical Reference Manual (ARM DDI 0460C ID021511)

  3. Versal ACAP Technical Reference Manual (AM011)