Sipeed M0S Dock

Overview

The M0S is a very small module measuring 10x11mm using the BL616 SoC as the main control chip, with the following features:

Tri-Mode Wireless: WiFi6 / BT 5.2 / Zigbee
High Frequency：320MHz default
Ultra-low Power Consumption：Wifi6 low power consumption feature
High speed USB：Support USB2.0 HS OTG，up to 480Mbps
Rich peripheral ports：Support RGB LCD，DVP Camera，Ethernet RMII and SDIO
Tiny Size：Place ceramic antenna on 10x11 mm tiny size, and route all IO out

The M0S Dock is a carrier board for the M0S module and pushes out some of its I/O pins.

Hardware

For more information about the Bouffalo Lab BL-61x MCU:

Supported Features

The maix_m0s_dock board supports the hardware features listed below.

on-chip / on-board: Feature integrated in the SoC / present on the board.
2 / 2: Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.
vnd,foo: Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

`maix_m0s_dock/bl616c50q2i` target

Type	Location	Description	Compatible
CPU	on-chip	Xuantie E907 Core CPU1	`xuantie,e907`
Clock control	on-chip	Generic fixed-rate clock provider2	`fixed-clock`
	on-chip	The BL61x WIFI PLL1	`bflb,bl61x-wifipll`
	on-chip	The BL61x Audio PLL1	`bflb,bl61x-aupll`
	on-chip	The BL61x Root Clock Represents both FCLK and HCLK, which should be kept the same1	`bflb,bl61x-root-clk`
	on-chip	The BCLK clock, or peripheral clock Source Clock -> Root Clock -> / divider -> BCLK1	`bflb,bclk`
	on-chip	The BL61x Flash Clock Source -> divider -> CLK Only has settings for Bank 1 (boot flash) at the moment1	`bflb,bl61x-flash-clk`
	on-chip	Bouffalolab BL61x Clock Controller1	`bflb,bl61x-clock-controller`
DMA	on-chip	Bouffalo Lab DMA1	`bflb,dma`
Flash controller	on-chip	Bouffalolab Flash Controller1	`bflb,flash-controller`
GPIO & Headers	on-chip	BouffaloLab GPIO node for BL61X serie1	`bflb,bl61x-gpio`
I2C	on-chip	Bouffalolab I2C interface1 1	`bflb,i2c`
Input	on-board	Group of GPIO-bound input keys1	`gpio-keys`
Interrupt controller	on-chip	Nuclei ECLIC interrupt controller1	`nuclei,eclic`
LED	on-board	Group of GPIO-controlled LEDs1	`gpio-leds`
Memory controller	on-chip	BL61x pseudo-static RAM controller1	`bflb,bl61x-psram`
MIPI-DBI	on-chip	BFLB MIPI DBI controller When used with devices that dont match MIPI DBI properly (eg commands are fully with DC set, not DC then data, for example SSD1327), you MUST use cs-gpios and dc-gpio to allow holding the lines for command via software and not use hardware DC and CS1	`bflb,dbi`
MTD	on-board	Flash node1	`soc-nv-flash`
MTD	on-board	Fixed partitions of a flash (or other non-volatile storage) memory1	`fixed-partitions`
Pin control	on-chip	Bouffalo Lab Pinctrl node1	`bflb,pinctrl`
Serial controller	on-chip	Bouffalo Lab UART1 1	`bflb,uart`
SPI	on-chip	Bouffalolab SPI1	`bflb,spi`
SRAM	on-chip	Generic on-chip SRAM2	`mmio-sram`
System controller	on-chip	BouffaloLab Efuse1	`bflb,efuse`
Timer	on-chip	RISC-V Machine Timer1	`riscv,machine-timer`

System Clock

The M0S (BL616) Dock Board is configured to run at maximum speed (320MHz) and can be overclocked to 480 MHz.

Serial Port

The maix_m0s_dock board uses UART0 as default serial port. It is connected to the pins on the side of the USB port.

Programming and Debugging

Samples

Build the Zephyr kernel and the Hello World sample application:

# From the root of the zephyr repository
west build -b maix_m0s_dock samples/hello_world
west flash

Run your favorite terminal program to listen for output. Under Linux the terminal should be /dev/ttyUSB0. For example:
```
$ screen /dev/ttyUSB0 115200
```
Connection should be configured as follows:
- Speed: 115200
- Data: 8 bits
- Parity: None
- Stop bits: 1
Then, unpower and re-power the board.
```
*** Booting Zephyr OS build v4.2.0 ***
Hello World! maix_m0s_dock/bl616c50q2i
```

Congratulations, you have maix_m0s_dock configured and running Zephyr.