Bouffalo Lab BL706-IoT-DVK
Overview
The BL706-IoT-DVK is a development board from Bouffalo Lab based on the BL706 (QFN48 package, BL706C00Q2I) RISC-V microcontroller. It features USB-C connectivity, four indicator LEDs, and exposes most GPIO pins for peripheral evaluation. A USB-to-serial backplane provides JTAG debugging and UART console access.
Hardware
The BL706C00Q2I SoC has the following features:
32-bit RISC-V core (SiFive E24) running at 144 MHz
132 KB SRAM (64 KB instruction TCM + 64 KB data TCM/cache + 4 KB retention)
4 MB external flash (XIP) on module
USB 2.0 FS device
2x UART, 1x SPI, 1x I2C, 1x I2S
5-channel PWM
12-bit ADC / 10-bit DAC
Hardware security engine (AES/SHA/TRNG)
Bluetooth Low Energy 5.0 / Zigbee
32 GPIO pins (QFN48 package)
The board provides:
USB-C connector (for power, USB device interface, and CDC-ACM console)
USB-to-serial backplane (for UART console and JTAG debugging)
4 indicator LEDs (TX0, RX0, TX1, RX1)
UART0 on GPIO14 (TX) / GPIO15 (RX)
UART1 on GPIO18 (TX) / GPIO19 (RX)
SPI on GPIO3 (SCLK) / GPIO4 (MOSI) / GPIO5 (MISO) / GPIO6 (SS)
I2C on GPIO5 (SDA) / GPIO6 (SCL) (shared with SPI, disabled by default)
Exposed GPIO headers for peripheral connections
Supported Features
The bl706_iot_dvk board supports the hardware features listed below.
- on-chip / on-board
- Feature integrated in the SoC / present on the board.
- 2 / 2
-
Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files. -
vnd,foo -
Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.
bl706_iot_dvk/bl706c00q2i target
Type |
Location |
Description |
Compatible |
|---|---|---|---|
CPU |
on-chip |
SiFive E24 Standard Core CPU1 |
|
ADC |
on-chip |
Bouffalolab ADC1 |
|
Bluetooth |
on-chip |
Bluetooth HCI for Bouffalo Lab BL70X1 |
|
Cache |
on-chip |
Bouffalo Lab L1C cache control1 |
|
Clock control |
on-chip |
||
on-chip |
Bouffalolab F32K clock1 |
||
on-chip |
The BL70x/L DLL1 |
||
on-chip |
Bouffalolab Root Clock Represents both FCLK and HCLK depending on their presence, which should be kept the same1 |
||
on-chip |
The BCLK clock, or peripheral clock Source -> / divider -> This Clock1 |
||
on-chip |
BFLB Flash Clock Source -> divider -> CLK Only has settings for Bank 1 on BL61x (boot flash) at the moment1 |
||
on-chip |
Bouffalolab BL70x(L) Clock Controller1 |
||
Counter |
on-chip |
Bouffalo Lab General Purpose Timer Block1 |
|
on-chip |
Bouffalo Lab Timer Channel (Counter)2 |
||
on-chip |
Bouffalo Lab RTC Counter (HBN-based)1 |
||
Cryptographic accelerator |
on-chip |
Bouffalo Lab SEC Engine TRNG (True Random Number Generator)1 |
|
on-chip |
Bouffalo Lab SEC Engine SHA hardware accelerator1 |
||
on-chip |
Bouffalo Lab SEC Engine AES hardware accelerator1 |
||
DMA |
on-chip |
Bouffalo Lab DMA1 |
|
Flash controller |
on-chip |
Bouffalolab Flash Controller1 |
|
GPIO & Headers |
on-chip |
Bouffalo Lab BL60x and BL70x GPIO node1 |
|
I2C |
on-chip |
Bouffalolab I2C interface1 |
|
Input |
on-chip |
Bouffalolab Infrared Receiver Peripheral Wire the output of a diode like VS1838B to the specified GPIO pin1 |
|
Interrupt controller |
on-chip |
RISC-V CPU interrupt controller1 |
|
on-chip |
RISC-V Core Local Interrupt Controller CLIC Pre-Standard v0.91 |
||
LED |
on-board |
Group of GPIO-controlled LEDs1 |
|
MTD |
on-board |
Flash node1 |
|
on-board |
Fixed partitions of a flash (or other non-volatile storage) memory1 |
||
Pin control |
on-chip |
Bouffalo Lab Pinctrl node1 |
|
Power management |
on-chip |
Bouffalolab Power Controller1 |
|
PWM |
on-chip |
Bouffalolab PWM 11 |
|
Regulator |
on-chip |
Bouffalolab HBN SoC (CPU, Memory, etc) voltage regulator It is a LDO with a canonical voltage of 1.10v It has two modes, but they are only switched between when going into sleep mode and do not share settings areas1 |
|
on-chip |
Bouffalolab HBN RT (RTC) voltage regulator It is a LDO with a canonical voltage of 1.10v It has two modes, but they are only switched between when going into sleep mode and do not share settings areas1 |
||
on-chip |
Bouffalolab HBN AON (Always ON section) voltage regulator It is a LDO with a canonical voltage of 1.10v It has two modes, but they are only switched between when going into sleep mode and do not share settings areas1 |
||
Serial controller |
on-chip |
||
SPI |
on-chip |
Bouffalolab SPI1 |
|
SRAM |
on-chip |
Generic on-chip SRAM3 |
|
System controller |
on-chip |
BouffaloLab Efuse1 |
|
Timer |
on-chip |
RISC-V Machine Timer1 |
|
USB |
on-chip |
Bouffalo Lab USB 1.1 Full-Speed device controller (v1 block)1 |
|
Watchdog |
on-chip |
Bouffalo Lab Watchdog Timer1 |
Connections and IOs
Default Zephyr Peripheral Mapping:
USB_DP : GPIO7
USB_DM : GPIO8
UART0_TX : GPIO14
UART0_RX : GPIO15
UART1_TX : GPIO18
UART1_RX : GPIO19
SPI0_SCLK : GPIO3
SPI0_MOSI : GPIO4
SPI0_MISO : GPIO5
SPI0_SS : GPIO6
I2C0_SDA : GPIO5 (shared with SPI)
I2C0_SCL : GPIO6 (shared with SPI)
TX0_LED : GPIO22
RX0_LED : GPIO29
TX1_LED : GPIO30
RX1_LED : GPIO31
Programming and Debugging
The bl706_iot_dvk board supports the runners and associated west commands listed below.
| flash | debug | |
|---|---|---|
| bflb_mcu_tool | ✅ (default) |
Building
# From the root of the zephyr repository
west build -b bl706_iot_dvk samples/hello_world
Flashing
The board can be flashed over UART using bflb-mcu-tool. Hold the Boot
button while pressing Reset to enter the bootloader, then run:
west flash
Console
By default the board uses a USB CDC-ACM UART as the Zephyr console. After flashing and resetting the board, the console is available on the USB serial port at 115200 baud.
Alternatively, UART0 is available via the USB-to-serial backplane for console access without USB CDC-ACM.