QEMU Emulation for ARM Cortex-M0

Board Overview

Name:

qemu_cortex_m0

Vendor:

Nordic Semiconductor

Status:

Maintained

Architecture:

arm

SoC:

nrf51822

Browse board sources

Overview

This board configuration will use QEMU to emulate the BBC Microbit (Nordic nRF51822) platform.

This configuration provides support for an ARM Cortex-M0 CPU and these devices:

• Nested Vectored Interrupt Controller

• TIMER (nRF TIMER System Clock)

Note

This board configuration makes no claims about its suitability for use with an actual nRF51 Microbit hardware system, or any other hardware system.

Hardware

Supported Features

The qemu_cortex_m0 board supports the hardware features listed below.

on-chip / on-board

Feature integrated in the SoC / present on the board.

2 / 2

Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.

vnd,foo

Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

qemu_cortex_m0/nrf51822 target

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-M0 CPU1	arm,cortex-m0
ADC	on-chip	nRF ADC node1	nordic,nrf-adc
ARM architecture	on-chip	Nordic UICR (User Information Configuration Registers)1	nordic,nrf-uicr
	on-chip	Nordic nRF family MPU (Memory Protection Unit)1	nordic,nrf-mpu
	on-chip	Nordic nRF family SWI (Software Interrupt)6	nordic,nrf-swi
Clock control	on-chip	Nordic nRF clock control node1	nordic,nrf-clock
	on-chip	Nordic nRF high-frequency crystal oscillator (nRF51 series)1	nordic,nrf51-hfxo
Comparator	on-chip	Nordic nRF LPCOMP (analog Low-Power COMParator)1	nordic,nrf-lpcomp
Counter	on-chip	Nordic nRF timer node3	nordic,nrf-timer
Cryptographic accelerator	on-chip	Nordic ECB (AES electronic codebook mode encryption)1	nordic,nrf-ecb
	on-chip	Nordic nRF family CCM (AES CCM mode encryption)1	nordic,nrf-ccm
Flash controller	on-chip	Nordic NVMC (Non-Volatile Memory Controller)1	nordic,nrf51-flash-controller
GPIO & Headers	on-chip	NRF5 GPIOTE1	nordic,nrf-gpiote
	on-chip	NRF5 GPIO1	nordic,nrf-gpio
I2C	on-chip	Nordic nRF family TWI (TWI master)2	nordic,nrf-twi
Interrupt controller	on-chip	ARMv6-M NVIC (Nested Vectored Interrupt Controller) controller1	arm,v6m-nvic
Miscellaneous	on-chip	Nordic FICR (Factory Information Configuration Registers)1	nordic,nrf-ficr
	on-chip	Nordic nRF family PPI (Programmable Peripheral Interconnect)1	nordic,nrf-ppi
MTD	on-chip	Flash node1	soc-nv-flash
	on-board	Fixed partitions of a flash (or other non-volatile storage) memory1	fixed-partitions
Networking	on-chip	Nordic nRF family RADIO peripheral1	nordic,nrf-radio
Pin control	on-chip	Nordic nRF family Pin Controller1	nordic,nrf-pinctrl
Power management	on-chip	Nordic nRF power control node1	nordic,nrf-power
PWM	on-chip	nRFx S/W PWM1	nordic,nrf-sw-pwm
Retained memory	on-chip	Nordic GPREGRET (General Purpose Register Retention) device1	nordic,nrf-gpregret
RNG	on-chip	Nordic nRF family RNG (Random Number Generator)1	nordic,nrf-rng
RTC	on-chip	Nordic nRF RTC (Real-Time Counter)2	nordic,nrf-rtc
Sensors	on-chip	Nordic nRF family TEMP node1	nordic,nrf-temp
	on-chip	Nordic nRF quadrature decoder (QDEC) node1	nordic,nrf-qdec
Serial controller	on-chip	Nordic nRF family UART1	nordic,nrf-uart
SPI	on-chip	Nordic nRF family SPI (SPI master)2	nordic,nrf-spi
SRAM	on-chip	Generic on-chip SRAM1	mmio-sram
Watchdog	on-chip	Nordic nRF family WDT (Watchdog Timer)1	nordic,nrf-wdt

Devices

System Clock

This board configuration uses a system clock frequency of 1 MHz.

Serial Port

This board configuration uses a single serial communication channel with the CPU’s UART0.

Known Problems or Limitations

The following platform features are unsupported:

• Writing to the hardware’s flash memory

Programming and Debugging

The qemu_cortex_m0 board supports the runners and associated west commands listed below.

	flash	debug

Use this configuration to run basic Zephyr applications and kernel tests in the QEMU emulated environment, for example, with the Basic Synchronization sample:

# From the root of the zephyr repository
west build -b qemu_cortex_m0 samples/synchronization
west build -t run

This will build an image with the synchronization sample app, boot it using QEMU, and display the following console output:

***** BOOTING ZEPHYR OS v1.8.99 - BUILD: Jun 27 2017 13:09:26 *****
threadA: Hello World from arm!
threadB: Hello World from arm!
threadA: Hello World from arm!
threadB: Hello World from arm!
threadA: Hello World from arm!
threadB: Hello World from arm!
threadA: Hello World from arm!
threadB: Hello World from arm!
threadA: Hello World from arm!
threadB: Hello World from arm!

Exit QEMU by pressing CTRL+A x.

Debugging

Refer to the detailed overview about Application Debugging.

Networking

References

1. The Definitive Guide to the ARM Cortex-M0, Second Edition by Joseph Yiu (ISBN 978-0-12-803278-7)

2. ARMv6-M Architecture Technical Reference Manual (ARM DDI 0419D 0403D ID051917)

3. Procedure Call Standard for the ARM Architecture (ARM IHI 0042E, current through ABI release 2.09, 2012/11/30)

4. Cortex-M0 Revision r2p1 Technical Reference Manual (ARM DDI 0432C ID113009)

5. Cortex-M0 Devices Generic User Guide (ARM DUI 0497A ID112109)