QEMU Emulation for ARCv2 & ARCv3
Overview
This board configuration will use QEMU to emulate set of generic ARCv2 and ARCv3 hardware platforms.
The following features of ARC ISA cores are currently supported:
CPU: * ARCv2 EM * ARCv2 HS3x * ARCv3 HS5x * ARCv3 HS6x
Only little-endian configurations
Full 32 register set
ARC core free-running timers/counters Timer0 & Timer1
ARC core interrupt controller with multiple priority levels
DW UART
5 slots for MMIO Virtio devices
Hardware
Supported Features
The qemu_arc board supports the hardware features listed below.
- on-chip / on-board
- Feature integrated in the SoC / present on the board.
- 2 / 2
-
Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files. -
vnd,foo -
Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.
qemu_arc/qemu_arc_em target
Type |
Location |
Description |
Compatible |
|---|---|---|---|
CPU |
on-board |
Synopsys ARC EM CPU1 |
|
Interrupt controller |
on-board |
ARCV2 interrupt controller1 |
|
MTD |
on-board |
Flash node1 |
|
Serial controller |
on-board |
ns16550 UART2 |
|
Timer |
on-board |
Synopsys ARC Local Timer with Interrupt Capabilities2 |
qemu_arc/qemu_arc_hs target
Type |
Location |
Description |
Compatible |
|---|---|---|---|
Interrupt controller |
on-board |
ARCV2 interrupt controller1 |
|
MTD |
on-board |
Flash node1 |
|
Serial controller |
on-board |
ns16550 UART2 |
|
Timer |
on-board |
Synopsys ARC Local Timer with Interrupt Capabilities2 |
qemu_arc/qemu_arc_hs/xip target
Type |
Location |
Description |
Compatible |
|---|---|---|---|
Interrupt controller |
on-board |
ARCV2 interrupt controller1 |
|
MTD |
on-board |
Flash node1 |
|
Serial controller |
on-board |
ns16550 UART2 |
|
Timer |
on-board |
Synopsys ARC Local Timer with Interrupt Capabilities2 |
qemu_arc/qemu_arc_hs5x target
Type |
Location |
Description |
Compatible |
|---|---|---|---|
Interrupt controller |
on-board |
ARCV2 interrupt controller1 |
|
MTD |
on-board |
Flash node1 |
|
Serial controller |
on-board |
ns16550 UART2 |
|
Timer |
on-board |
Synopsys ARC Local Timer with Interrupt Capabilities2 |
qemu_arc/qemu_arc_hs6x target
Type |
Location |
Description |
Compatible |
|---|---|---|---|
Interrupt controller |
on-board |
ARCV2 interrupt controller1 |
|
MTD |
on-board |
Flash node1 |
|
Serial controller |
on-board |
ns16550 UART2 |
|
Timer |
on-board |
Synopsys ARC Local Timer with Interrupt Capabilities2 |
Devices
System Clock
This board configuration uses a system clock frequency of 1 MHz.
Serial Port
This board configuration uses a single serial communication channel with the DesignWare UART.
Known Problems or Limitations
The following platform features are unsupported:
Memory-protection unit (MPU)
MMIO Virtio Ethernet
Programming and Debugging
The qemu_arc board supports the runners and associated west commands listed below.
| flash | debug | debugserver | |
|---|---|---|---|
| qemu | ✅ (default) | ✅ (default) | ✅ |
Use this configuration to run basic Zephyr applications and kernel tests in the QEMU
emulated environment, for example, with the Basic Synchronization sample
(note you may use qemu_arc/qemu_em, qemu_arc/qemu_hs, qemu_arc/qemu_hs5x or
qemu_arc/qemu_hs6x depending on target CPU):
# From the root of the zephyr repository
west build -b qemu_arc/qemu_em samples/synchronization
west build -t run
This will build an image with the synchronization sample app, boot it using QEMU, and display the following console output:
*** Booting Zephyr OS build zephyr-v2.2.0-2486-g7dbfcf4bab57 ***
threadA: Hello World from qemu_arc!
threadB: Hello World from qemu_arc!
threadA: Hello World from qemu_arc!
threadB: Hello World from qemu_arc!
Exit QEMU by pressing CTRL+A x.
Debugging
Refer to the detailed overview about Application Debugging.
References
- 1.`Programmer’s Reference Manual for ARC HS