QEMU Emulation for ARM Cortex-R5

Board Overview

Name:

qemu_cortex_r5

Vendor:

QEMU, a generic and open source machine emulator and virtualizer

Status:

Not actively maintained

Architecture:

arm

SoC:

zynqmp_rpu

Browse board sources

Overview

This board configuration will use QEMU to emulate the Xilinx Zynq UltraScale+ (ZynqMP) platform.

This configuration provides support for an ARM Cortex-R5 CPU and these devices:

• ARM PL-390 Generic Interrupt Controller

• Xilinx Zynq TTC (Cadence TTC)

• Xilinx Zynq UART

Note

This board configuration makes no claims about its suitability for use with an actual ZCU102 hardware system, or any other hardware system.

Hardware

Supported Features

The qemu_cortex_r5 board supports the hardware features listed below.

on-chip / on-board

Feature integrated in the SoC / present on the board.

2 / 2

Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.

vnd,foo

Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

qemu_cortex_r5/zynqmp_rpu target

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-R5F CPU1	arm,cortex-r5f
EDAC	on-chip	Xilinx ZynqMP DDR memory controller1	xlnx,zynqmp-ddrc-2.40a
Ethernet	on-chip	Xilinx GEM Ethernet controller4	xlnx,gem
GPIO & Headers	on-chip	Xilinx Zynq-7000/ZynqMP MIO/EMIO GPIO Controller1	xlnx,ps-gpio
	on-chip	Xilinx Zynq-7000/ZynqMP MIO/EMIO GPIO Controller bank6	xlnx,ps-gpio-bank
I2C	on-chip	Cadence I2C controller2	cdns,i2c
Interrupt controller	on-chip	ARM Generic Interrupt Controller v11	arm,gic-v1
IPM	on-chip	The Xilinx IPI(Inter Processor Interrupt) mailbox controller is to manage messaging between two Xilinx Zynq UltraScale+ MPSoC IPI agents2	xlnx,zynqmp-ipi-mailbox
MTD	on-chip	Flash node1	soc-nv-flash
Pin control	on-chip	Xilinx ZynqMP SoC Pin Controller1	xlnx,pinctrl-zynqmp
Serial controller	on-chip	Xilinx PS UART11	xlnx,xuartps
SPI	on-chip	Cadence SPI controller2	cdns,spi
SRAM	on-board	Generic on-chip SRAM1	mmio-sram
Timer	on-chip	Xilinx PS Triple-Timer Counter13	xlnx,ttcps

Devices

System Timer

This board configuration uses a system timer tick frequency of 1000 Hz.

Serial Port

This board configuration uses a single serial communication channel with the on-chip UART0.

Known Problems or Limitations

The following platform features are unsupported:

• Dual-redundant Core Lock-step (DCLS) execution is not emulated.

• Xilinx Zynq TTC driver does not support tickless mode operation.

Programming and Debugging

The qemu_cortex_r5 board supports the runners and associated west commands listed below.

	flash	debug

Use this configuration to run basic Zephyr applications and kernel tests in the QEMU emulated environment, for example, with the Basic Synchronization sample:

# From the root of the zephyr repository
west build -b qemu_cortex_r5 samples/synchronization
west build -t run

This will build an image with the synchronization sample app, boot it using QEMU, and display the following console output:

*** Booting Zephyr OS build v2.2.0  ***
threadA: Hello World from qemu_cortex_r5!
threadB: Hello World from qemu_cortex_r5!
threadA: Hello World from qemu_cortex_r5!
threadB: Hello World from qemu_cortex_r5!
threadA: Hello World from qemu_cortex_r5!
threadB: Hello World from qemu_cortex_r5!
threadA: Hello World from qemu_cortex_r5!
threadB: Hello World from qemu_cortex_r5!
threadA: Hello World from qemu_cortex_r5!
threadB: Hello World from qemu_cortex_r5!

Exit QEMU by pressing CTRL+A x.

Debugging

Refer to the detailed overview about Application Debugging.

References

1. ARMv7-A and ARMv7-R Architecture Reference Manual (ARM DDI 0406C ID051414)

2. Cortex-R5 and Cortex-R5F Technical Reference Manual (ARM DDI 0460C ID021511)

3. Zynq UltraScale+ Device Technical Reference Manual (UG1085)