QEMU Emulation for ARM Cortex-M3

Overview

This board configuration will use QEMU to emulate the TI LM3S6965 platform.

This configuration provides support for an ARM Cortex-M3 CPU and these devices:

Nested Vectored Interrupt Controller
System Tick System Clock
Stellaris UART

Note

This board configuration makes no claims about its suitability for use with an actual ti_lm3s6965 hardware system, or any other hardware system.

Hardware

Supported Features

The qemu_cortex_m3 board supports the hardware features listed below.

on-chip / on-board: Feature integrated in the SoC / present on the board.
2 / 2: Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.
vnd,foo: Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

`qemu_cortex_m3/ti_lm3s6965` target

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-M3 CPU1	`arm,cortex-m3`
Clock control	on-chip	Generic fixed-rate clock provider1	`fixed-clock`
Ethernet	on-chip	TI Stellaris Ethernet1	`ti,stellaris-ethernet`
Flash controller	on-chip	TI Stellaris flash controller1	`ti,stellaris-flash-controller`
GPIO & Headers	on-chip	TI Stellaris GPIO7	`ti,stellaris-gpio`
Interrupt controller	on-chip	ARMv7-M NVIC (Nested Vectored Interrupt Controller)1	`arm,v7m-nvic`
MTD	on-chip	Flash node1	`soc-nv-flash`
Serial controller	on-chip	TI Stellaris UART3	`ti,stellaris-uart`
SRAM	on-chip	Generic on-chip SRAM1	`mmio-sram`
Timer	on-chip	ARMv7-M System Tick1	`arm,armv7m-systick`

Devices

System Clock

This board configuration uses a system clock frequency of 12 MHz.

Serial Port

This board configuration uses a single serial communication channel with the CPU’s UART0.

If SLIP networking is enabled (see below), an additional serial port will be used for it.

Known Problems or Limitations

The following platform features are unsupported:

Memory protection through optional MPU. However, using a XIP kernel effectively provides TEXT/RODATA write protection in ROM.
SRAM at addresses 0x1FFF0000-0x1FFFFFFF
Writing to the hardware’s flash memory

Programming and Debugging

The qemu_cortex_m3 board supports the runners and associated west commands listed below.

	flash	debug

Use this configuration to run basic Zephyr applications and kernel tests in the QEMU emulated environment, for example, with the Basic Synchronization sample:

# From the root of the zephyr repository
west build -b qemu_cortex_m3 samples/synchronization
west build -t run

This will build an image with the synchronization sample app, boot it using QEMU, and display the following console output:

***** BOOTING ZEPHYR OS v1.8.99 - BUILD: Jun 27 2017 13:09:26 *****
threadA: Hello World from arm!
threadB: Hello World from arm!
threadA: Hello World from arm!
threadB: Hello World from arm!
threadA: Hello World from arm!
threadB: Hello World from arm!
threadA: Hello World from arm!
threadB: Hello World from arm!
threadA: Hello World from arm!
threadB: Hello World from arm!

Exit QEMU by pressing CTRL+A x.

Debugging

Refer to the detailed overview about Application Debugging.

Networking

The board supports SLIP networking over an emulated serial port (CONFIG_NET_SLIP_TAP=y). The detailed setup is described in Networking with QEMU.

It is also possible to use the QEMU built-in Ethernet adapter to connect to the host system. This is faster than using SLIP and is also the preferred way. See Networking with QEMU Ethernet for details.

References

The Definitive Guide to the ARM Cortex-M3, Second Edition by Joseph Yiu (ISBN 978-0-12-382090-7)
ARMv7-M Architecture Technical Reference Manual (ARM DDI 0403D ID021310)
Procedure Call Standard for the ARM Architecture (ARM IHI 0042E, current through ABI release 2.09, 2012/11/30)
Cortex-M3 Revision r2p1 Technical Reference Manual (ARM DDI 0337I ID072410)
Cortex-M3 Devices Generic User Guide (ARM DUI 0052A ID121610)