QEMU Emulation for ARM Cortex-A53

Overview

This board configuration will use QEMU to emulate a generic Cortex-A53 hardware platform.

This configuration provides support for an ARM Cortex-A53 CPU and these devices:

GIC-400 interrupt controller
ARM architected timer
PL011 UART controller

Hardware

Supported Features

The qemu_cortex_a53 board supports the hardware features listed below.

on-chip / on-board: Feature integrated in the SoC / present on the board.
2 / 2: Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.
vnd,foo: Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

`qemu_cortex_a53/qemu_cortex_a53` target

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-A53 CPU2	`arm,cortex-a53`
Clock control	on-chip	Generic fixed-rate clock provider1	`fixed-clock`
Ethernet	on-board	Intel E1000 Ethernet controller1	`intel,e1000`
Interrupt controller	on-chip	ARM Generic Interrupt Controller v31	`arm,gic-v3`
Interrupt controller	on-chip	GIC v3 Interrupt Translation Service1	`arm,gic-v3-its`
PCIe	on-chip	PCIe Controller in ECAM mode1	`pci-host-ecam-generic`
Power management CPU operations	on-board	Power State Coordination Interface (PSCI) version 0.21	`arm,psci-0.2`
Serial controller	on-chip	ARM PL011 UART1	`arm,pl011`
SRAM	on-board	Generic on-chip SRAM1	`mmio-sram`
Timer	on-chip	per-core ARM architected timer1	`arm,armv8-timer`
Virtio	on-board	VIRTIO over MMIO32	`virtio,mmio`

`qemu_cortex_a53/qemu_cortex_a53/smp` target

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-A53 CPU2	`arm,cortex-a53`
Clock control	on-chip	Generic fixed-rate clock provider1	`fixed-clock`
Ethernet	on-board	Intel E1000 Ethernet controller1	`intel,e1000`
Interrupt controller	on-chip	ARM Generic Interrupt Controller v31	`arm,gic-v3`
Interrupt controller	on-chip	GIC v3 Interrupt Translation Service1	`arm,gic-v3-its`
PCIe	on-chip	PCIe Controller in ECAM mode1	`pci-host-ecam-generic`
Power management CPU operations	on-board	Power State Coordination Interface (PSCI) version 0.21	`arm,psci-0.2`
Serial controller	on-chip	ARM PL011 UART1	`arm,pl011`
SRAM	on-board	Generic on-chip SRAM1	`mmio-sram`
Timer	on-chip	per-core ARM architected timer1	`arm,armv8-timer`
Virtio	on-board	VIRTIO over MMIO32	`virtio,mmio`

Devices

System Clock

This board configuration uses a system clock frequency of 62.5 MHz.

Serial Port

This board configuration uses a single serial communication channel with the CPU’s UART0.

Known Problems or Limitations

The following platform features are unsupported:

Writing to the hardware’s flash memory

Programming and Debugging

The qemu_cortex_a53 board supports the runners and associated west commands listed below.

	flash	debug

Use this configuration to run basic Zephyr applications and kernel tests in the QEMU emulated environment, for example, with the Basic Synchronization sample:

# From the root of the zephyr repository
west build -b qemu_cortex_a53 samples/synchronization
west build -t run

This will build an image with the synchronization sample app, boot it using QEMU, and display the following console output:

***** Booting Zephyr OS build zephyr-v2.0.0-1657-g99d310da48e5 *****
threadA: Hello World from qemu_cortex_a53!
threadB: Hello World from qemu_cortex_a53!
threadA: Hello World from qemu_cortex_a53!
threadB: Hello World from qemu_cortex_a53!
threadA: Hello World from qemu_cortex_a53!
threadB: Hello World from qemu_cortex_a53!
threadA: Hello World from qemu_cortex_a53!
threadB: Hello World from qemu_cortex_a53!

Exit QEMU by pressing CTRL+A x.

Debugging

Refer to the detailed overview about Application Debugging.

Networking

The board supports the QEMU built-in Ethernet adapter to connect to the host system. See Networking with QEMU Ethernet for details.

It is also possible to use SLIP networking over an emulated serial port. Although this board only supports a single UART, so subsystems like logging and shell would need to be disabled, therefore this is not directly supported.

References

(ID050815) ARM® Cortex®-A Series - Programmer’s Guide for ARMv8-A
(ID070919) Arm® Architecture Reference Manual - Armv8, for Armv8-A architecture profile
(ARM DAI 0527A) Application Note Bare-metal Boot Code for ARMv8-A Processors
AArch64 Exception and Interrupt Handling
Fundamentals of ARMv8-A