Tang Mega 138K Pro Dock

Overview

The Tang Mega 138K Pro Dock [1] is an FPGA development board from Sipeed based on the Gowin GW5AST-LV138 device. It combines a large FPGA fabric with an integrated 32-bit RISC-V AndesTech AE350 [2] SoC and provides interfaces such as DDR3, PCIe Gen3 x4, SFP+, Gigabit Ethernet, HDMI/DVI, MIPI CSI, and M.2.

Hardware

The Tang Mega 138K Pro Dock provides the following hardware features:

Andes AE350 32-bit RISC-V processor
1 GB DDR3 memory
2 x 128 Mbit SPI flash
1 x 8 Kbit I2C EPROM
PCIe connector
2 x SFP+ connectors
Gigabit Ethernet
2 x DVI TX interface
2 x DVI RX interface
DVP interface
RGB interface
2 x MIPI CSI connectors
2 x ADC
2 x MS5351 Clock generator
MicroSD card slot
M.2 Key-B socket
3 x PMOD connectors
1 x Customizable USB-C connector
40-pin expansion header
3.5 mm headphone jack
Speaker connector
Mic Array interface
WS2812 RGB LED and aRGB/WS2812 strip connector
PWM fan connector
JTAG and UART debug interfaces
User LEDs and buttons

Supported Features

The tang_mega_138k_pro_dock board supports the hardware features listed below.

on-chip / on-board: Feature integrated in the SoC / present on the board.
2 / 2: Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.
vnd,foo: Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

`tang_mega_138k_pro_dock/ae350` target

On-target memory for this board target: 1 GiB of RAM, 10 MiB of Flash.

Type	Location	Description	Compatible
CPU	on-chip	Andes Technology RISC-V core from the AndesCore v5 series1	`andestech,andescore-v5`
Cache	on-chip	AndesTech L2 cache1	`andestech,l2c`
Clock control	on-chip	Generic fixed-rate clock provider1	`fixed-clock`
Counter	on-chip	This is a representation of the Andes Technology atcpit100 PIT node1	`andestech,atcpit100`
DMA	on-chip	Andes DMA controller channel: a phandle to the DMA controller plus the following four integer cells:1	`andestech,atcdmacx00`
GPIO & Headers	on-chip	Andes Technology ATCGPIO100 GPIO Controller1	`andestech,atcgpio100`
I2C	on-chip	AndesTech ATCIIC100 I2C1	`andestech,atciic100`
Interrupt controller	on-chip	RISC-V CPU interrupt controller1	`riscv,cpu-intc`
Interrupt controller	on-chip	SiFive RISCV-V platform-local interrupt controller2	`sifive,plic-1.0.0`
Mailbox	on-chip	AndesTech MBOX PLIC-SW1	`andestech,mbox-plic-sw`
MTD	on-board	Flash node1	`soc-nv-flash`
Serial controller	on-chip	ns16550 UART2	`ns16550`
SPI	on-chip	This binding gives a representation of Andes ATCSPI200 SPI controller1	`andestech,atcspi200`
SRAM	on-chip	Generic on-chip SRAM1	`mmio-sram`
System controller	on-chip	System Controller Registers R/W1	`syscon`
Timer	on-chip	RISC-V Machine Timer1	`riscv,machine-timer`
Watchdog	on-chip	Andes Watchdog driver1	`andestech,atcwdt200`

`tang_mega_138k_pro_dock/ae350/demo` target

On-target memory for this board target: 256 MiB of RAM, 10 MiB of Flash.

Type	Location	Description	Compatible
CPU	on-chip	Andes Technology RISC-V core from the AndesCore v5 series1	`andestech,andescore-v5`
Cache	on-chip	AndesTech L2 cache1	`andestech,l2c`
Clock control	on-chip	Generic fixed-rate clock provider1	`fixed-clock`
Counter	on-chip	This is a representation of the Andes Technology atcpit100 PIT node1	`andestech,atcpit100`
DMA	on-chip	Andes DMA controller channel: a phandle to the DMA controller plus the following four integer cells:1	`andestech,atcdmacx00`
GPIO & Headers	on-chip	Andes Technology ATCGPIO100 GPIO Controller1	`andestech,atcgpio100`
I2C	on-chip	AndesTech ATCIIC100 I2C1	`andestech,atciic100`
Input	on-board	Group of GPIO-bound input keys1	`gpio-keys`
Interrupt controller	on-chip	RISC-V CPU interrupt controller1	`riscv,cpu-intc`
Interrupt controller	on-chip	SiFive RISCV-V platform-local interrupt controller2	`sifive,plic-1.0.0`
LED	on-board	Group of GPIO-controlled LEDs1	`gpio-leds`
Mailbox	on-chip	AndesTech MBOX PLIC-SW1	`andestech,mbox-plic-sw`
MTD	on-board	Flash node1	`soc-nv-flash`
Serial controller	on-chip	ns16550 UART1 1	`ns16550`
SPI	on-chip	This binding gives a representation of Andes ATCSPI200 SPI controller1	`andestech,atcspi200`
SRAM	on-chip	Generic on-chip SRAM1	`mmio-sram`
System controller	on-chip	System Controller Registers R/W1	`syscon`
Timer	on-chip	RISC-V Machine Timer1	`riscv,machine-timer`
Watchdog	on-chip	Andes Watchdog driver1	`andestech,atcwdt200`

The demo variant supports the peripherals enabled by the ae350_demo FPGA IP configuration in the Modified Reference Design [3]:

UART2 as the console
GPIO for LEDs and buttons
Watchdog
RTC
PIT

Programming and debugging

The tang_mega_138k_pro_dock board supports the runners and associated west commands listed below.

	flash	debug	attach	debugserver	rtt
openfpgaloader	✅ (default)
openocd	✅	✅ (default)	✅	✅	✅

FPGA provisioning

Before using board, write the matching FPGA bitstream to offset zero of the external flash. For the demo variant, build the ae350_demo.fs image from the Modified Reference Design [3] and program it as follows:

openFPGALoader --board tangmega138k --external-flash --write-flash \
  --offset 0x0 ae350_demo.fs

This step creates the AE350 processor and peripherals described by the selected variant’s devicetree. Repeat it after the FPGA image has been erased or replaced.

Building and flashing Zephyr

You can build applications in the usual way. Here is an example for the Blinky application.

Zephyr firmware is programmed via the FTDI JTAG adapter connected to the JTAG|UART interface on the board. For the XIP configuration, west flash writes only zephyr.bin to the firmware area reserved by the board runner; it does not program the FPGA image.

# From the root of the zephyr repository
west build -b tang_mega_138k_pro_dock/ae350/demo samples/basic/blinky
west flash

Debugging

The AE350 is debugged via its dedicated JTAG port on the 40-pin connector (J23). A separate JTAG adapter compatible with OpenOCD is required.

The AE350 JTAG pins are:

JTAG Function	Pin number
TMS	5
TCK	6
TRST	7
TDO	8
TDI	9

The default Tang Mega 138K Pro Dock configuration uses XIP. Flash the application before starting a debug session, then attach without loading it again because the XIP flash mapping is read-only to the debugger:

# From the root of the zephyr repository
west build -b tang_mega_138k_pro_dock/ae350/demo samples/basic/blinky
west attach

For early-boot debugging, set CONFIG_XIP=n in the application configuration and build a non-XIP image. Non-XIP images are linked at the selected SRAM address and west debug loads the ELF directly into RAM:

# From the root of the zephyr repository
west build -b tang_mega_138k_pro_dock/ae350/demo samples/basic/blinky
west debug