Sipeed M1S Dock

Overview

The Sipeed M1S Dock is a development board based on the Bouffalo Lab BL808 tri-core SoC. The BL808 integrates three RISC-V CPUs, Wi-Fi, BLE 5.0, and a hardware security engine.

The M1S Dock includes a 16 MB flash (W25Q128JV), USB-C connector, two user buttons, one user LED, and exposes GPIO pins for peripheral access.

Hardware

SoC: BL808 tri-core RISC-V
- M0: T-Head E907 (RV32IMAFCP, 320 MHz) — supported by Zephyr
- D0: T-Head C906 (RV64IMAFCV, 480 MHz) — not yet supported
- LP: T-Head E902 (RV32EMC, 160 MHz) — not yet supported
RAM: 224 KB SRAM
Flash: 16 MB SPI NOR (W25Q128JV)
LED: 1 user LED on GPIO8
Buttons: 2 user buttons on GPIO22 and GPIO23
Console: UART0 at 115200 baud

For more information about the Bouffalo Lab BL808 SoC:

Bouffalo Lab BL808 Datasheet

Supported Features

The m1s_dock board supports the hardware features listed below.

on-chip / on-board: Feature integrated in the SoC / present on the board.
2 / 2: Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.
vnd,foo: Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

`m1s_dock/bl808c09q2i` target

Type	Location	Description	Compatible
CPU	on-chip	Xuantie E907 Core CPU1	`xuantie,e907`
ADC	on-chip	Bouffalolab ADC1	`bflb,adc`
Clock control	on-chip	Generic fixed-rate clock provider3 1	`fixed-clock`
	on-chip	Bouffalolab F32K clock1	`bflb,f32k`
	on-chip	Bouffalolab PLL settings1 2	`bflb,pll`
	on-chip	Bouffalolab Root Clock Represents both FCLK and HCLK depending on their presence, which should be kept the same2	`bflb,root-clk`
	on-chip	The BCLK clock, or peripheral clock Source -> / divider -> This Clock1	`bflb,bclk`
	on-chip	BFLB Flash Clock Source -> divider -> CLK Only has settings for Bank 1 on BL61x (boot flash) at the moment1	`bflb,flash-clk`
	on-chip	Bouffalolab BL808 Clock Controller1	`bflb,bl808-clock-controller`
Counter	on-chip	Bouffalo Lab General Purpose Timer Block1	`bflb,timer`
	on-chip	Bouffalo Lab Timer Channel (Counter)2	`bflb,timer-channel`
	on-chip	Bouffalo Lab RTC Counter (HBN-based)1	`bflb,rtc`
Cryptographic accelerator	on-chip	Bouffalo Lab SEC Engine TRNG (True Random Number Generator)1	`bflb,sec-eng-trng`
	on-chip	Bouffalo Lab SEC Engine SHA hardware accelerator1	`bflb,sec-eng-sha`
	on-chip	Bouffalo Lab SEC Engine AES hardware accelerator1	`bflb,sec-eng-aes`
DMA	on-chip	Bouffalo Lab DMA1	`bflb,dma`
Flash controller	on-chip	Bouffalolab Flash Controller1	`bflb,flash-controller`
GPIO & Headers	on-chip	BouffaloLab BL61x/BL808 GPIO1	`bflb,bl61x_808-gpio`
I2C	on-chip	Bouffalolab I2C interface1 1	`bflb,i2c`
Input	on-chip	Bouffalolab Infrared Receiver Peripheral Wire the output of a diode like VS1838B to the specified GPIO pin1	`bflb,irx`
Input	on-board	Group of GPIO-bound input keys1	`gpio-keys`
Interrupt controller	on-chip	Nuclei ECLIC interrupt controller1	`nuclei,eclic`
LED	on-board	Group of GPIO-controlled LEDs1	`gpio-leds`
LED	on-board	Group of PWM-controlled LEDs1	`pwm-leds`
MTD	on-board	Flash node1	`soc-nv-flash`
MTD	on-board	Fixed partitions of a flash (or other non-volatile storage) memory1	`fixed-partitions`
Pin control	on-chip	Bouffalo Lab Pinctrl node1	`bflb,pinctrl`
Power management	on-chip	Bouffalolab Power Controller1	`bflb,power-controller`
PWM	on-chip	Bouffalolab PWM 21	`bflb,pwm-2`
Regulator	on-chip	Bouffalolab HBN SoC (CPU, Memory, etc) voltage regulator It is a LDO with a canonical voltage of 1.10v It has two modes, but they are only switched between when going into sleep mode and do not share settings areas1	`bflb,soc-regulator`
	on-chip	Bouffalolab HBN RT (RTC) voltage regulator It is a LDO with a canonical voltage of 1.10v It has two modes, but they are only switched between when going into sleep mode and do not share settings areas1	`bflb,rt-regulator`
	on-chip	Bouffalolab HBN AON (Always ON section) voltage regulator It is a LDO with a canonical voltage of 1.10v It has two modes, but they are only switched between when going into sleep mode and do not share settings areas1	`bflb,aon-regulator`
Sensors	on-chip	Bouffalo Lab internal die temperature sensor (TSEN)1	`bflb,tsen`
Serial controller	on-chip	Bouffalo Lab UART2	`bflb,uart`
SPI	on-chip	Bouffalolab SPI1	`bflb,spi`
SRAM	on-chip	Generic on-chip SRAM2	`mmio-sram`
System controller	on-chip	BouffaloLab Efuse1	`bflb,efuse`
Timer	on-chip	RISC-V Machine Timer1	`riscv,machine-timer`
Watchdog	on-chip	Bouffalo Lab Watchdog Timer1	`bflb,wdt`

System Clock

The BL808 default clock configuration:

M0 (E907): 320 MHz (WIFIPLL)
D0 (C906): 480 MHz (WIFIPLL) — not yet supported
LP (E902): 160 MHz — not yet supported

Serial Port

The m1s_dock board uses UART0 as the default serial port, accessible via the USB-C connector.

Programming and Debugging

The m1s_dock board supports the runners and associated west commands listed below.

	flash	debug
bflb_mcu_tool	✅ (default)

Flashing

Build and flash the Hello World sample application:

# From the root of the zephyr repository
west build -b m1s_dock samples/hello_world
west flash

Run your favorite terminal program to listen for output. For example:
```
$ minicom -D /dev/ttyACM0 -o
```
Connection should be configured as follows:
- Speed: 115200
- Data: 8 bits
- Parity: None
- Stop bits: 1
Then, press and release the RST button:
```
*** Booting Zephyr OS build v4.3.0 ***
Hello World! m1s_dock/bl808c09q2i
```