Ai-Thinker M64P-32S Development Board

Board Overview

Ai-Thinker M64P-32S Development Board

Name:

ai_m64p_32s_kit

Vendor:

Ai-Thinker Co., Ltd.

Status:

Maintained

Architecture:

riscv

SoC:

bl616cl4855

Browse board sources

Overview

Ai-M64P-32S is a Wi-Fi 6 + BLE5.3 module developed by Shenzhen Ai-Thinker Technology Co., Ltd. The module is equipped with the BL616CL chip as the core processor, supports Wi-Fi 802.11b/g/n/ax protocol and BLE protocol, and supports Thread protocol. The BL616CL system includes a low-power, high-performance 32-bit RISC-V CPU with floating-point unit, DSP unit (P extension), 16KB ICache, 8KB DCache, and 388KB of memory.

Hardware

Ai-M64P-32S-Kit provides the following hardware components:

• Ai-M64P-32S module with BL616CL, and two internal buck regulators controlled by GPIO2 and GPIO3

• Five total LEDs:

  • RGB LEDs on GPIO14, 15, and 16

  • Warm White LED on GPIO28

  • Cold White LED on GPIO27

• Two Buttons:

  • Reset Button (EN)

  • Boot Select Button (BOOT)

• CH340C USB to UART adapter.

For more information about the Bouffalo Lab BL616CL MCU:

• Bouffalo Lab BL616CL MCU Datasheet

• Bouffalo Lab Development Zone

• ai_m64p_32s_kit Schematics

Supported Features

The ai_m64p_32s_kit board supports the hardware features listed below.

on-chip / on-board

Feature integrated in the SoC / present on the board.

2 / 2

Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.

vnd,foo

Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

ai_m64p_32s_kit/bl616cl4855 target

On-target memory for this board target: 384 KiB of RAM, 4 MiB of Flash.

Type	Location	Description	Compatible
CPU	on-chip	Xuantie E907 Core CPU1	xuantie,e907
Clock control	on-chip	Generic fixed-rate clock provider31	fixed-clock
	on-chip	Bouffalolab F32K clock1	bflb,f32k
	on-chip	Bouffalolab PLL settings1	bflb,pll
	on-chip	Bouffalolab Root Clock Represents both FCLK and HCLK depending on their presence, which should be kept the same1	bflb,root-clk
	on-chip	The BCLK clock, or peripheral clock Source -> / divider -> This Clock1	bflb,bclk
	on-chip	BFLB Flash Clock Source -> divider -> CLK Only has settings for Bank 1 on BL61x (boot flash) at the moment1	bflb,flash-clk
	on-chip	Bouffalolab BL616CL Clock Controller1	bflb,bl616cl-clock-controller
Counter	on-chip	Bouffalo Lab RTC Counter (HBN-based)1	bflb,rtc
Cryptographic accelerator	on-chip	Bouffalo Lab SEC Engine TRNG (True Random Number Generator)1	bflb,sec-eng-trng
	on-chip	Bouffalo Lab SEC Engine SHA hardware accelerator1	bflb,sec-eng-sha
	on-chip	Bouffalo Lab SEC Engine AES hardware accelerator1	bflb,sec-eng-aes
DMA	on-chip	Bouffalo Lab DMA1	bflb,dma
GPIO & Headers	on-chip	BouffaloLab BL61x/BL808 GPIO1	bflb,bl61x_808-gpio
I2C	on-chip	Bouffalolab I2C interface11	bflb,i2c
Input	on-board	Group of GPIO-bound input keys1	gpio-keys
Interrupt controller	on-chip	Nuclei ECLIC interrupt controller1	nuclei,eclic
LED	on-board	Group of GPIO-controlled LEDs1	gpio-leds
	on-board	Group of PWM-controlled LEDs1	pwm-leds
Memory controller	on-chip	Serial Flash controller1	bflb,sf-controller
	on-chip	Serial Flash Controller Bank11	bflb,sf-bank
	on-chip	BL61x pseudo-static RAM controller1	bflb,bl61x-psram
MIPI-DBI	on-chip	BFLB MIPI DBI controller When used with devices that dont match MIPI DBI properly (eg commands are fully with DC set, not DC then data, for example SSD1327), you MUST use cs-gpios and dc-gpio to allow holding the lines for command via software and not use hardware DC and CS1	bflb,dbi
MTD	on-board	Bouffalolab Serial Flash controller Flash1	bflb,sf-flash
OTP memory	on-chip	BouffaloLab Efuse1	bflb,efuse
Pin control	on-chip	Bouffalo Lab Pinctrl node1	bflb,pinctrl
Power management	on-chip	Bouffalolab Power Controller1	bflb,power-controller
PWM	on-chip	Bouffalolab PWM 21	bflb,pwm-2
SDHC	on-chip	Bouffalo Lab SD Host Controller1	bflb,sdhc
Serial controller	on-chip	Bouffalo Lab UART12	bflb,uart
SPI	on-chip	Bouffalolab SPI11	bflb,spi
SRAM	on-chip	Generic on-chip SRAM12	mmio-sram
Timer	on-chip	RISC-V Machine Timer1	riscv,machine-timer
Watchdog	on-chip	Bouffalo Lab Watchdog Timer1	bflb,wdt

System Clock

The M64P (BL616CL) Development Board is configured to run at maximum speed (320MHz).

Serial Port

The ai_m64p_32s_kit board uses UART0 as default serial port. It is connected to USB Serial converter and port is used for both program and console.

Programming and Debugging

Samples

1. Build the Zephyr kernel and the Hello World sample application:

   # From the root of the zephyr repository
   west build -b ai_m64p_32s_kit samples/hello_world
   west flash
   

2. Run your favorite terminal program to listen for output. Under Linux the terminal should be /dev/ttyUSB0. For example:

   $ screen /dev/ttyUSB0 115200
   

   Connection should be configured as follows:

   • Speed: 115200

   • Data: 8 bits

   • Parity: None

   • Stop bits: 1

   Then, press and release RST button

   *** Booting Zephyr OS build v4.4.0 ***
   Hello World! ai_m64p_32s_kit/bl616cl4855
   

Congratulations, you have ai_m64p_32s_kit configured and running Zephyr.